Simulation Results: rv_dm/use_dmi_interface

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.58 %
  • code
  • 73.62 %
  • assert
  • 96.66 %
  • func
  • 92.46 %
  • block
  • 89.69 %
  • line
  • 89.73 %
  • branch
  • 72.02 %
  • toggle
  • 70.22 %
  • FSM
  • 62.50 %
Validation stages
V1
92.59%
V2
69.57%
V2S
85.71%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 47.000s 998.629us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 49.000s 474.773us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 46.000s 223.279us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 48.000s 2942.772us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 50.000s 152.076us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 52.000s 3532.239us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 45.000s 3033.906us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 45.000s 3890.196us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 66.000s 37077.119us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 53.000s 778.455us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 48.000s 154.357us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 51.000s 152.836us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 42.000s 249.297us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 46.000s 138.507us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 52.000s 261.145us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 41.000s 333.426us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 48.000s 1484.459us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 53.000s 778.455us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 41.000s 677.595us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 49.000s 254.501us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 51.000s 152.836us 1 1 100.00
rom_read_access 0 1 0.00
rv_dm_rom_read_access 39.000s 44.757us 0 1 0.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 50.000s 1045.618us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 41.000s 85.962us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 88.000s 11039.561us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 64.000s 4443.894us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 48.000s 153.532us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 64.000s 4443.894us 1 1 100.00
rv_dm_csr_rw 41.000s 85.962us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 40.000s 127.435us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 43.000s 85.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 47.000s 998.629us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 49.000s 337.056us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 51.000s 168.068us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 36.000s 196.305us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 38.000s 950.056us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 47.000s 1948.455us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 52.000s 277.822us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 35.000s 976.690us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 56.000s 3317.040us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 49.000s 148.241us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 46.000s 4637.372us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 43.000s 176.616us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 51.000s 234.547us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm 42.000s 5555.215us 1 1 100.00
rv_dm_tap_fsm_rand_reset 105.000s 3507.839us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 46.000s 146.772us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 44.000s 190.241us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 38.000s 70.416us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 46.000s 354.392us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 46.000s 354.392us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 64.000s 4443.894us 1 1 100.00
rv_dm_csr_hw_reset 50.000s 1045.618us 1 1 100.00
rv_dm_csr_rw 41.000s 85.962us 1 1 100.00
rv_dm_same_csr_outstanding 52.000s 753.878us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 64.000s 4443.894us 1 1 100.00
rv_dm_csr_hw_reset 50.000s 1045.618us 1 1 100.00
rv_dm_csr_rw 41.000s 85.962us 1 1 100.00
rv_dm_same_csr_outstanding 52.000s 753.878us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 46.000s 1304.833us 1 1 100.00
rv_dm_tl_intg_err 46.000s 3020.629us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 46.000s 3020.629us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 46.000s 4637.372us 1 1 100.00
rv_dm_debug_disabled 47.000s 80.594us 0 1 0.00
sec_cm_lc_dft_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 46.000s 4637.372us 1 1 100.00
rv_dm_debug_disabled 47.000s 80.594us 0 1 0.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 47.000s 998.629us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 47.000s 691.663us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 45.000s 134.548us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 45.000s 134.548us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 47.000s 691.663us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 44.000s 953.598us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 215.000s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:481) [scoreboard] sba_tl_access_q item uncompared: 2 test runs
rv_dm_sba_tl_access 74572891874035133231694070591583276661731689428761394871661977252206526045754 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23897
rv_dm_bad_sba_tl_access 66860796092560716850793052346374989628613570693440893640968742797991013596702 93
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23805
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp 2 test runs
rv_dm_delayed_resp_sba_tl_access 90279103231963538646430504335813342409046244729464531327594902882417457515023 107
UVM_INFO @ 277821971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 100949928169251840715406358823897237522993006248404219638821922192472788385839 107
UVM_INFO @ 3317040027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*]) 2 test runs
rv_dm_hart_unavail 28279623249559123163212715006733885097666635444170209148655567405963371989099 87
UVM_INFO @ 234547166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 87491526215350486747404691658447967364452298040934491649015748563955053057907 88
UVM_INFO @ 190241108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*]) 1 test run
rv_dm_mem_tl_access_resuming 49900601741083553820668510065033240341884593052428377383573910794017339072341 87
UVM_INFO @ 249296562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) 1 test run
rv_dm_jtag_dmi_debug_disabled 65230130261342967038526462280627707737713171040259171245744062516465111679702 87
UVM_INFO @ 148241438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=*, but it was *"}. Item: (req: (cip_tl_seq_item@23900) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } 1 test run
rv_dm_rom_read_access 31850081374928540324971423779254163695668328436862822229236481946549732006906 87
).
UVM_INFO @ 44756684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_rv_dm_sva_*/rv_dm_enable_checker.sv,42): Assertion DebugRequestNeedsDebug_A has failed 1 test run
rv_dm_debug_disabled 80045517263847553710109257447476141162316372144033804112665391202067460965215 90
UVM_ERROR @ 80594499 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)
UVM_INFO @ 80594499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rv_dm_scanmode 6185845843920430583154050041334346189332495236730998465521213856835058488630 87
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [rv_dm_common_vseq] Check failed (vseq_done) 1 test run
rv_dm_stress_all_with_rand_reset 109711839493685203798470968447828594466998912739691719746521455210081299387328 101
UVM_INFO @ 953597713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---