Simulation Results: otp_ctrl

 
08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.35 %
  • code
  • 71.65 %
  • assert
  • 93.90 %
  • func
  • 51.50 %
  • line
  • 87.33 %
  • branch
  • 83.89 %
  • cond
  • 85.73 %
  • toggle
  • 67.14 %
  • FSM
  • 34.14 %
Validation stages
V1
88.89%
V2
60.00%
V2S
55.56%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 3.320s 808.900us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 24.130s 6128.220us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.170s 146.954us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.040s 46.151us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 14.260s 1449.280us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.290s 140.168us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.120s 62.563us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.040s 46.151us 1 1 100.00
otp_ctrl_csr_aliasing 3.290s 140.168us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.310s 42.808us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.430s 561.177us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 172.860s 13553.410us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 4.800s 307.304us 0 1 0.00
partition_check 0 2 0.00
otp_ctrl_background_chks 3.740s 197.117us 0 1 0.00
otp_ctrl_check_fail 4.410s 143.773us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 6.400s 464.773us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 11.260s 677.199us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 4.820s 122.950us 0 1 0.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 8.310s 699.360us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.110s 98.872us 0 1 0.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 20.510s 765.096us 0 1 0.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 14.950s 2997.356us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 31.670s 5321.393us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 122.070s 63010.465us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.290s 47.732us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.560s 119.707us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 14.050s 3373.987us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 14.050s 3373.987us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.170s 146.954us 1 1 100.00
otp_ctrl_csr_rw 2.040s 46.151us 1 1 100.00
otp_ctrl_csr_aliasing 3.290s 140.168us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.770s 185.926us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.170s 146.954us 1 1 100.00
otp_ctrl_csr_rw 2.040s 46.151us 1 1 100.00
otp_ctrl_csr_aliasing 3.290s 140.168us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.770s 185.926us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
otp_ctrl_tl_intg_err 13.470s 1146.063us 0 1 0.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
otp_ctrl_tl_intg_err 13.470s 1146.063us 0 1 0.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 24.130s 6128.220us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 24.130s 6128.220us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.110s 98.872us 0 1 0.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_lci_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.110s 98.872us 0 1 0.00
sec_cm_kdi_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.110s 98.872us 0 1 0.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.110s 98.872us 0 1 0.00
otp_ctrl_macro_errs 14.950s 2997.356us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.110s 98.872us 0 1 0.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.110s 98.872us 0 1 0.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.110s 98.872us 0 1 0.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_lci_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.110s 98.872us 0 1 0.00
sec_cm_kdi_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.110s 98.872us 0 1 0.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.110s 98.872us 0 1 0.00
otp_ctrl_macro_errs 14.950s 2997.356us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.110s 98.872us 0 1 0.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.110s 98.872us 0 1 0.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 4.800s 307.304us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 4.410s 143.773us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 11.260s 677.199us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 11.260s 677.199us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 11.260s 677.199us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 11.260s 677.199us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 11.260s 677.199us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 24.130s 6128.220us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 11.260s 677.199us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 24.130s 6128.220us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 394.250s 15961.865us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 6.400s 464.773us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 24.130s 6128.220us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 24.130s 6128.220us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 14.950s 2997.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 134.430s 63021.624us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 43.580s 1713.986us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 3 test runs
otp_ctrl_background_chks 7295135938483264420698835901086157615479591603379998701579974304481374636167 816
UVM_INFO @ 197116731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 75603903330878602801172724611488609602104078318111821780505709993183656692726 838
UVM_INFO @ 98872450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 58995084873973376774657633307199481974428610884072117905043463221047097968482 1390
UVM_INFO @ 122950085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 2 test runs
otp_ctrl_low_freq_read 45119253942392706133911248589255231816330888178538092089595549274513720074597 95
UVM_INFO @ 63021623635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 54384022387198431162738394808554558272685605399957735288287552044344498145608 1230
UVM_INFO @ 63010464553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 80742579084951504373384796099351103123512011123035088956845484665564587253626 112893
UVM_INFO @ 13553410339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_init_fail 62252880020674560130212971461320234555303346283178821236388187585355647139947 2789
UVM_INFO @ 307304387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:419) scoreboard [scoreboard] Waited * cycles but did not see alert fatal_check_error. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
otp_ctrl_dai_errs 19200177352645656387115047861026458536112249826988398602634319728015081556043 11004
UVM_INFO @ 765096469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 70420289472437830171732961472561588821135728157945342899405173186663503878729 1016
UVM_INFO @ 143772538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:2202) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 27559385637468592802599497153459501261348080327487346206195011480319301619841 25078
UVM_INFO @ 1713985683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_bus_integ_error) did not fire in * cycles. 1 test run
otp_ctrl_tl_intg_err 115164691515179857113808409188695238294418035684193309545642493603777838877748 223
UVM_INFO @ 1146062668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:786) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 6157770544631271860728869832358772421474212233876647914700623148738432483093 97
UVM_INFO @ 62563098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---