Simulation Results

Simulation Results: i2c

10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
88.24 %

code
85.60 %

assert
97.25 %

func
81.88 %

block
95.90 %

line
95.23 %

branch
92.63 %

toggle
72.52 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		82.93%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	142.000s	1365.281us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	13.000s	1826.190us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	26.431us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	2.000s	17.046us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	8.000s	2542.807us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	69.365us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	65.612us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	2.000s	17.046us	1	1	100.00
	i2c_csr_aliasing	2.000s	69.365us	1	1	100.00

34/41 passed

82.93 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.000s	5.702us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	3601.000s	0.000us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	2117.000s	32088.428us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	17.426us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	3373.000s	12334.259us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1861.000s	3118.735us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	3.000s	381.190us	1	1	100.00
	i2c_host_fifo_fmt_empty	106.000s	454.968us	1	1	100.00
	i2c_host_fifo_reset_rx	4.000s	295.185us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	127.000s	15848.349us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	12.000s	2886.089us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.000s	14.205us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	5.000s	688.932us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	2815.000s	21940.633us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	7.000s	687.286us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	15.000s	1611.370us	1	1	100.00
	i2c_target_intr_smoke	9.000s	4131.386us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	3.000s	467.800us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	470.598us	1	1	100.00
target_fifo_full				1	3	33.33
	i2c_target_stress_wr	3600.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	15.000s	1611.370us	1	1	100.00
	i2c_target_intr_stress_wr	3601.000s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	9.000s	12114.041us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	194.000s	3859.885us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	10.000s	4590.973us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	17.000s	10668.126us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.000s	390.980us	1	1	100.00
	i2c_target_fifo_watermarks_tx	3.000s	276.486us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	2117.000s	32088.428us	1	1	100.00
	i2c_host_perf_precise	9.000s	244.299us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	12.000s	2886.089us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.000s	51.338us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	4.000s	503.679us	1	1	100.00
	i2c_target_nack_acqfull_addr	5.000s	2774.016us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	158.844us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	8.000s	943.456us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	4.000s	1019.061us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	38.034us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	28.257us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	246.065us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	246.065us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	26.431us	1	1	100.00
	i2c_csr_rw	2.000s	17.046us	1	1	100.00
	i2c_csr_aliasing	2.000s	69.365us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	29.887us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	26.431us	1	1	100.00
	i2c_csr_rw	2.000s	17.046us	1	1	100.00
	i2c_csr_aliasing	2.000s	69.365us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	29.887us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	56.929us	1	1	100.00
	i2c_sec_cm	2.000s	42.125us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	56.929us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	23.000s	1241.144us	1
target_error_intr				1
	i2c_target_unexp_stop	3.000s	706.526us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	2.000s	22.034us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				3 test runs
	i2c_host_stress_all	6372185763261481227329032264085180182424973643279182864791271028805027226302	None
	i2c_target_stress_wr	73778076307965630256286695622740890553478392858619084722634675799648421138394	None
	i2c_target_intr_stress_wr	70111910985710521551419643811719958218639778145053187546887287502433632625318	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	76105169963580801140150617828176839739939601370382835206146207015338048955317	89	UVM_INFO @ 5702280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	4131986683498960934394506129031730556044290105525543611293288023470480940342	94	UVM_INFO @ 22034149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	17274686568026791996547053386891182617283549027950259839776543648707938601398	93	UVM_INFO @ 688931748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/i2c-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_i2c_/rtl/i2c_fifos.sv,320): Assertion TxWriteStableBeforeHandshake_A has failed (* cycles, starting * PS)				1 test run
	i2c_target_unexp_stop	18099683828332473287637510595133915310513762201910046831550583107583773318972	89	UVM_ERROR @ 706525772 ps: (i2c_fifos.sv:320) [ASSERT FAILED] TxWriteStableBeforeHandshake_A UVM_INFO @ 706525772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	51512178907478455416131221714980889368705055385268673445661993958392070614092	88	UVM_INFO @ 10668126239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	22542736752225556088774847894649127872949471871393950175398292006563990311384	98	UVM_INFO @ 1241143534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead				1 test run
	i2c_host_mode_toggle	67184856984159035601784570604561696737241241484870775352606809292349755462005	96	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------