Simulation Results

Simulation Results: rv_dm/use_dmi_interface

14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
87.45 %

code
73.70 %

assert
96.90 %

func
91.74 %

block
89.75 %

line
89.73 %

branch
72.17 %

toggle
70.39 %

FSM
62.50 %

Validation stages

V1		92.59%
V2		69.57%
V2S		85.71%
V3		0.00%
unmapped		0.00%

25/27 passed

92.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	52.000s	1933.882us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	35.000s	341.432us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	46.000s	357.361us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	115.000s	42186.582us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	43.000s	1087.418us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	45.000s	3776.738us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	57.000s	16067.510us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	46.000s	82.148us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	57.000s	8615.309us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	41.000s	256.887us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	36.000s	212.938us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	51.000s	263.174us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	51.000s	51.332us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	38.000s	224.097us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	42.000s	80.486us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	41.000s	96.351us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	45.000s	523.725us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	41.000s	256.887us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	50.000s	180.267us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	51.000s	473.353us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	51.000s	263.174us	1	1	100.00
rom_read_access				0	1	0.00
	rv_dm_rom_read_access	36.000s	71.692us	0	1	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	47.000s	718.300us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	47.000s	289.446us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	110.000s	7887.507us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	56.000s	301.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	41.000s	69.194us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	56.000s	301.000us	1	1	100.00
	rv_dm_csr_rw	47.000s	289.446us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	41.000s	127.968us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	40.000s	102.879us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	52.000s	1933.882us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	42.000s	147.591us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	49.000s	718.417us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	47.000s	133.608us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	47.000s	915.282us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	48.000s	9690.200us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	52.000s	278.039us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	58.000s	14626.239us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	47.000s	65.023us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	57.000s	138.975us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	48.000s	1240.746us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	49.000s	243.076us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	39.000s	185.224us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	58.000s	6338.736us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	93.000s	3284.383us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	46.000s	56.105us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	42.000s	826.469us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	47.000s	94.623us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	46.000s	160.740us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	46.000s	160.740us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	56.000s	301.000us	1	1	100.00
	rv_dm_csr_hw_reset	47.000s	718.300us	1	1	100.00
	rv_dm_csr_rw	47.000s	289.446us	1	1	100.00
	rv_dm_same_csr_outstanding	55.000s	138.711us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	56.000s	301.000us	1	1	100.00
	rv_dm_csr_hw_reset	47.000s	718.300us	1	1	100.00
	rv_dm_csr_rw	47.000s	289.446us	1	1	100.00
	rv_dm_same_csr_outstanding	55.000s	138.711us	1	1	100.00

V2S

6/7 passed

85.71 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	45.000s	782.571us	1	1	100.00
	rv_dm_tl_intg_err	54.000s	2058.031us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	54.000s	2058.031us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				1	2	50.00
	rv_dm_sba_debug_disabled	48.000s	1240.746us	1	1	100.00
	rv_dm_debug_disabled	46.000s	45.494us	0	1	0.00
sec_cm_lc_dft_en_intersig_mubi				1	2	50.00
	rv_dm_sba_debug_disabled	48.000s	1240.746us	1	1	100.00
	rv_dm_debug_disabled	46.000s	45.494us	0	1	0.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	52.000s	1933.882us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	52.000s	232.040us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	40.000s	257.671us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	40.000s	257.671us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	52.000s	232.040us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	51.000s	1054.235us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	223.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:481) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	74689561053663383220208155537905983292521326041997542916378820790061865027593	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10083
	rv_dm_bad_sba_tl_access	41979401119838700237584071824955539255743134139574701975664045701933503548319	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24309
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	69007074631828017037895517992309863147570046204176037277623871004773662233958	107	UVM_INFO @ 278039086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	13550771573497401984620080747035451898900584290769196336423113868188444701090	107	UVM_INFO @ 65022590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				2 test runs
	rv_dm_mem_tl_access_resuming	40717960007767534668944114399450901313574443041457903622305043884326732344785	87	UVM_INFO @ 51331666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	29899664762851250411130760244509139384428949217161107365600935780610432942735	93	UVM_INFO @ 1054234837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				2 test runs
	rv_dm_hart_unavail	23125314750854422743242700216506256668271860708128946814929815564519809445377	87	UVM_INFO @ 185224094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	35355933725933156395412917294280860524215035551158126711428553589288478210348	90	UVM_INFO @ 826468870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	18958816381924712146464646767239227264336874278872167808932141888344603855236	87	UVM_INFO @ 138974643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23890) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	43385133366053033116398753343326118686503830083156583344782458407226619227928	87	). UVM_INFO @ 71691744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_rv_dm_sva_/rv_dm_enable_checker.sv,42): Assertion DebugRequestNeedsDebug_A has failed				1 test run
	rv_dm_debug_disabled	25138080297227659886332784463547016779536864298491968080657500065825084776458	91	UVM_ERROR @ 45494009 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output) UVM_INFO @ 45494009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	15795168762263726706597826156658966444857365695539617319965232345448516003962	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---