Simulation Results: spi_device/1r1w

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.45 %
  • code
  • 89.51 %
  • assert
  • 95.40 %
  • func
  • 68.45 %
  • block
  • 98.33 %
  • line
  • 98.74 %
  • branch
  • 96.98 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 310.000s 23394.382us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 92.612us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 44.360us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 36.000s 3871.590us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.000s 276.987us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 5.000s 849.774us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 44.360us 1 1 100.00
spi_device_csr_aliasing 5.000s 276.987us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 13.851us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 17.680us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 18.175us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 14.935us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 6.551us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 44.137us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 44.137us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 24.000s 1622.469us 1 1 100.00
spi_device_tpm_sts_read 2.000s 80.732us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 22.000s 2598.791us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 6.000s 170.249us 1 1 100.00
spi_device_flash_all 12.000s 1146.654us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.000s 259.798us 1 1 100.00
spi_device_flash_all 12.000s 1146.654us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.000s 259.798us 1 1 100.00
spi_device_flash_all 12.000s 1146.654us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 12.000s 1146.654us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.000s 88.760us 1 1 100.00
spi_device_flash_all 12.000s 1146.654us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.000s 88.760us 1 1 100.00
spi_device_flash_all 12.000s 1146.654us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.000s 88.760us 1 1 100.00
spi_device_flash_all 12.000s 1146.654us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.000s 88.760us 1 1 100.00
spi_device_flash_all 12.000s 1146.654us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.000s 88.760us 1 1 100.00
spi_device_flash_all 12.000s 1146.654us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 43.000s 16206.905us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 82.000s 25995.535us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 82.000s 25995.535us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 82.000s 25995.535us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 14.000s 1029.243us 1 1 100.00
spi_device_read_buffer_direct 28.000s 1364.477us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 82.000s 25995.535us 1 1 100.00
spi_device_flash_all 12.000s 1146.654us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 12.000s 1146.654us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 12.000s 1146.654us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 7.000s 1031.187us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 7.000s 1031.187us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 228.000s 74767.749us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 310.000s 23394.382us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 493.000s 61172.917us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 686.000s 35048.993us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 21.130us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 14.557us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 5.000s 705.382us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 5.000s 705.382us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 92.612us 1 1 100.00
spi_device_csr_rw 3.000s 44.360us 1 1 100.00
spi_device_csr_aliasing 5.000s 276.987us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 577.055us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 92.612us 1 1 100.00
spi_device_csr_rw 3.000s 44.360us 1 1 100.00
spi_device_csr_aliasing 5.000s 276.987us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 577.055us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 3.000s 188.947us 1 1 100.00
spi_device_tl_intg_err 19.000s 1335.504us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 19.000s 1335.504us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 30835331433993818921169620787649570450355791598975774011420481252149110449859 87
UVM_ERROR @ 12026136 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[962] not found within the scope .
UVM_ERROR @ 12026136 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[962] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 113598921630892276264747859585136745238077142200682663268092273174611098634810 85
UVM_ERROR @ 3669966 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3af [1110101111] vs 0x0 [0])
UVM_ERROR @ 3729966 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x175 [101110101] vs 0x0 [0])
UVM_ERROR @ 3820966 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x14b [101001011] vs 0x0 [0])
UVM_ERROR @ 3869966 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1ec [111101100] vs 0x0 [0])