Simulation Results

Simulation Results: i2c

16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
88.38 %

code
86.45 %

assert
97.46 %

func
81.22 %

block
96.30 %

line
95.73 %

branch
93.39 %

toggle
72.52 %

FSM
84.17 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	153.000s	6422.608us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	7.000s	2002.408us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	37.071us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	19.317us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.000s	1390.506us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	67.160us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	51.783us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	19.317us	1	1	100.00
	i2c_csr_aliasing	2.000s	67.160us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.000s	25.776us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	3602.129s	0.000us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	60.000s	5279.572us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	2.000s	18.522us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	3466.000s	3359.422us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	909.000s	1682.205us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	3.000s	183.884us	1	1	100.00
	i2c_host_fifo_fmt_empty	14.000s	460.537us	1	1	100.00
	i2c_host_fifo_reset_rx	5.000s	114.800us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	195.000s	6854.791us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	14.000s	2874.551us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	3.000s	106.690us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	6.000s	489.215us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	2441.000s	35427.585us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	6.000s	847.123us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	76.000s	1875.613us	1	1	100.00
	i2c_target_intr_smoke	10.000s	1369.837us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	330.033us	1	1	100.00
	i2c_target_fifo_reset_tx	2.000s	182.773us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	3601.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	76.000s	1875.613us	1	1	100.00
	i2c_target_intr_stress_wr	1874.000s	14298.802us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	9.000s	1035.591us	1	1	100.00
target_clock_stretch				0	1	0.00
	i2c_target_stretch	10.000s	10048.950us	0	1	0.00
bad_address				1	1	100.00
	i2c_target_bad_addr	6.000s	4216.465us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	26.000s	10031.997us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	5.000s	1028.312us	1	1	100.00
	i2c_target_fifo_watermarks_tx	3.000s	109.615us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	60.000s	5279.572us	1	1	100.00
	i2c_host_perf_precise	28.000s	2559.840us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	14.000s	2874.551us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.000s	105.535us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	5.000s	3520.112us	1	1	100.00
	i2c_target_nack_acqfull_addr	5.000s	512.515us	1	1	100.00
	i2c_target_nack_txstretch	2.000s	756.479us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	8.000s	457.312us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	4.000s	2075.714us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	18.577us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	18.970us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	316.478us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	316.478us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	37.071us	1	1	100.00
	i2c_csr_rw	1.000s	19.317us	1	1	100.00
	i2c_csr_aliasing	2.000s	67.160us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	87.810us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	37.071us	1	1	100.00
	i2c_csr_rw	1.000s	19.317us	1	1	100.00
	i2c_csr_aliasing	2.000s	67.160us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	87.810us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	150.755us	1	1	100.00
	i2c_sec_cm	2.000s	216.236us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	150.755us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	12.000s	2338.813us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	748.172us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	12.000s	674.923us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	2737912609973304450971085248184726195374471511603491549078719857232827699041	97	UVM_INFO @ 25775842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	98396357790080847689619899728299988267953311149843346913989434833851340040323	110	UVM_INFO @ 674923357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				2 test runs
	i2c_host_stress_all	112414129856170036575499112020123295929545941977574661031559121713078374623345	None
	i2c_target_stress_wr	11227477332378209914595455941227569754624824365275864862660324796606932112815	None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	108715224859231878650968487470264444596654704481240780544286385761637191308667	93	UVM_INFO @ 489214598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!				1 test run
	i2c_target_stretch	75695695235971204789258277913758592056547404066385561833182521973023167697238	87	UVM_INFO @ 10048950251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/i2c-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_i2c_/rtl/i2c_fifos.sv,320): Assertion TxWriteStableBeforeHandshake_A has failed (* cycles, starting * PS)				1 test run
	i2c_target_unexp_stop	43301195584229991492549065102698090757290094648291869420963638748372286571442	89	UVM_ERROR @ 748171888 ps: (i2c_fifos.sv:320) [ASSERT FAILED] TxWriteStableBeforeHandshake_A UVM_INFO @ 748171888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	41020335049479293585978041303667943576992750928209241596413194689508800424691	88	UVM_INFO @ 10031997271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	93497539868691934483222866313310729671555921403427012956661493564390947289729	95	UVM_INFO @ 2338813018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---