Simulation Results: otp_ctrl

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.63 %
  • code
  • 72.26 %
  • assert
  • 93.95 %
  • func
  • 54.68 %
  • line
  • 87.53 %
  • branch
  • 84.37 %
  • cond
  • 86.16 %
  • toggle
  • 65.01 %
  • FSM
  • 38.23 %
Validation stages
V1
100.00%
V2
65.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.670s 110.652us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 10.350s 407.260us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 4.040s 110.609us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.380s 61.304us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 12.700s 2717.197us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.180s 68.848us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.060s 133.807us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.380s 61.304us 1 1 100.00
otp_ctrl_csr_aliasing 3.180s 68.848us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.260s 573.658us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.150s 64.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 145.590s 5685.896us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.650s 190.862us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 3.240s 142.165us 0 1 0.00
otp_ctrl_check_fail 22.990s 2410.062us 1 1 100.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 7.590s 238.024us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 19.680s 924.309us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 46.390s 2453.973us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 23.880s 2431.362us 1 1 100.00
otp_ctrl_parallel_lc_esc 32.430s 17417.800us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 14.050s 291.781us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 4.870s 423.215us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 19.980s 1254.952us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 40.560s 2773.788us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.310s 57.603us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 3.670s 1136.241us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 8.670s 331.898us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 8.670s 331.898us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.040s 110.609us 1 1 100.00
otp_ctrl_csr_rw 2.380s 61.304us 1 1 100.00
otp_ctrl_csr_aliasing 3.180s 68.848us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.440s 121.508us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.040s 110.609us 1 1 100.00
otp_ctrl_csr_rw 2.380s 61.304us 1 1 100.00
otp_ctrl_csr_aliasing 3.180s 68.848us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.440s 121.508us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
otp_ctrl_tl_intg_err 20.580s 922.272us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 20.580s 922.272us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 10.350s 407.260us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 10.350s 407.260us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 32.430s 17417.800us 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.430s 17417.800us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.430s 17417.800us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 32.430s 17417.800us 1 1 100.00
otp_ctrl_macro_errs 4.870s 423.215us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.430s 17417.800us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 32.430s 17417.800us 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 32.430s 17417.800us 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.430s 17417.800us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.430s 17417.800us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 32.430s 17417.800us 1 1 100.00
otp_ctrl_macro_errs 4.870s 423.215us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.430s 17417.800us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 32.430s 17417.800us 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.650s 190.862us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 22.990s 2410.062us 1 1 100.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 19.680s 924.309us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 19.680s 924.309us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 19.680s 924.309us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 19.680s 924.309us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 19.680s 924.309us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 10.350s 407.260us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 19.680s 924.309us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 10.350s 407.260us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 503.740s 20098.339us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 7.590s 238.024us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 10.350s 407.260us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 10.350s 407.260us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 4.870s 423.215us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 120.080s 62680.762us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 30.390s 6655.509us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_partition_walk 35665045932357715231487350115807351938376948215785029072563622761749503352847 160061
UVM_INFO @ 5685895603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 30969965969570471539217640064195431619973672849504070219859241486583967006338 4454
UVM_INFO @ 238024402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 2 test runs
otp_ctrl_dai_lock 52171165998616651476913889512241055269703225439822029485479469207855362573220 11066
UVM_INFO @ 924308523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 55001523732947225673929277591664555239832991252847150544667896719779633196286 24939
UVM_INFO @ 2453973018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_macro_error has unexpected timeout error 2 test runs
otp_ctrl_macro_errs 19625557718732842118098691349588927697425351335001015877598556194888810769269 995
UVM_INFO @ 423214896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 103103256956299102759092255620046318614235846208811535065095884534248425654908 22996
UVM_INFO @ 2773787597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 65282944047155052448055843414849451857155130786021928491468616944391364281544 95
UVM_INFO @ 62680762084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 1 test run
otp_ctrl_background_chks 89978889856104653282874344733503853398035886222738386903713594119991490738974 974
UVM_INFO @ 142165369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr c* rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 68820353731274867611866990698667922767686214866114299572960397836554827201931 101
UVM_INFO @ 6655508955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---