Simulation Results: rv_dm/use_dmi_interface

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 86.55 %
  • code
  • 73.62 %
  • assert
  • 96.74 %
  • func
  • 89.29 %
  • block
  • 89.41 %
  • line
  • 89.37 %
  • branch
  • 71.25 %
  • toggle
  • 71.35 %
  • FSM
  • 62.50 %
Validation stages
V1
88.89%
V2
60.87%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 54.000s 4821.332us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 40.000s 332.901us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 46.000s 397.961us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 42.000s 17639.809us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 41.000s 461.924us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 52.000s 3172.353us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 78.000s 16014.094us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 65.000s 18964.853us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 49.000s 4615.273us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 54.000s 1386.241us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 44.000s 290.919us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 45.000s 208.642us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 40.000s 109.494us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 49.000s 111.498us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 48.000s 185.273us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 45.000s 283.164us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 46.000s 352.316us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 54.000s 1386.241us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 36.000s 272.660us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 50.000s 1263.745us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 45.000s 208.642us 1 1 100.00
rom_read_access 0 1 0.00
rv_dm_rom_read_access 43.000s 109.995us 0 1 0.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 47.000s 559.643us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 51.000s 188.420us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 79.000s 2238.679us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 51.000s 1214.617us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
rv_dm_csr_mem_rw_with_rand_reset 39.000s 93.294us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 51.000s 1214.617us 1 1 100.00
rv_dm_csr_rw 51.000s 188.420us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 43.000s 140.216us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 38.000s 92.649us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 54.000s 4821.332us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 46.000s 232.537us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 46.000s 572.226us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 38.000s 277.038us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 43.000s 2424.396us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 51.000s 2843.585us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 44.000s 58.545us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 51.000s 4965.839us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 55.000s 4788.054us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 56.000s 123.304us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 51.000s 3326.979us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 49.000s 124.466us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 32.000s 75.308us 0 1 0.00
tap_ctrl_transitions 0 2 0.00
rv_dm_tap_fsm 40.000s 24.961us 0 1 0.00
rv_dm_tap_fsm_rand_reset 42.000s 53.486us 0 1 0.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 52.000s 145.258us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 46.000s 464.469us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 40.000s 64.919us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 43.000s 781.464us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 43.000s 781.464us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 51.000s 1214.617us 1 1 100.00
rv_dm_csr_hw_reset 47.000s 559.643us 1 1 100.00
rv_dm_csr_rw 51.000s 188.420us 1 1 100.00
rv_dm_same_csr_outstanding 45.000s 669.408us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 51.000s 1214.617us 1 1 100.00
rv_dm_csr_hw_reset 47.000s 559.643us 1 1 100.00
rv_dm_csr_rw 51.000s 188.420us 1 1 100.00
rv_dm_same_csr_outstanding 45.000s 669.408us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 43.000s 700.714us 1 1 100.00
rv_dm_tl_intg_err 49.000s 3719.075us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 49.000s 3719.075us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 51.000s 3326.979us 1 1 100.00
rv_dm_debug_disabled 37.000s 167.731us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 51.000s 3326.979us 1 1 100.00
rv_dm_debug_disabled 37.000s 167.731us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 54.000s 4821.332us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 51.000s 242.548us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 51.000s 271.004us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 51.000s 271.004us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 51.000s 242.548us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 51.000s 61.307us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 528.000s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:487) [scoreboard] sba_tl_access_q item uncompared: 3 test runs
rv_dm_sba_tl_access 23312521521363852202327426556725007252591784386317423885658352713349918290146 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @24942
rv_dm_bad_sba_tl_access 78276535969280907549746953467105006119410078208899457380778847684201904840958 114
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @25145
rv_dm_autoincr_sba_tl_access 23478546598315329494712338484224324810475893562750645220390554784027292402886 111
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @25175
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) 2 test runs
rv_dm_jtag_dmi_debug_disabled 112865719409680403779847459046690706076929746887479432591108331872847192587490 87
UVM_INFO @ 123303860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 106551685603585423790989188676839431266238344426735917000732510660689638000496 89
UVM_INFO @ 464469222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_base_vseq.sv:139) virtual_sequencer [seq] m_mode_sequencer not configured. 1 test run
rv_dm_tap_fsm 27500294103100013134563870897511291030534905383024012269543177771074378800813 88
UVM_INFO @ 24961045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp 1 test run
rv_dm_delayed_resp_sba_tl_access 22188279366100921344441056563792713242741294738727717035251713218554531643081 107
UVM_INFO @ 58545407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_base_vseq.sv:139) virtual_sequencer [rv_dm_tap_fsm_vseq] m_mode_sequencer not configured. 1 test run
rv_dm_tap_fsm_rand_reset 92557632799823954099292250742819120634359556972312835592129403526943083937825 90
UVM_INFO @ 53485988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*]) 1 test run
rv_dm_mem_tl_access_resuming 20857698749851708067390255146979721530487115322794424072420460545317554796607 87
UVM_INFO @ 109494468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*]) 1 test run
rv_dm_hart_unavail 63150957641639542571464804116406103782058419579811071560378083947687439284628 87
UVM_INFO @ 75307634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:415) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=*, but it was *"}. Item: (req: (cip_tl_seq_item@24934) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } 1 test run
rv_dm_rom_read_access 59630141177789392397154457049368017394125080157672234461168115796518878884044 87
).
UVM_INFO @ 109994599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rv_dm_scanmode 5538084853420803206058245313105328092247871238364483840277899367622950057238 87
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_base_vseq.sv:139) virtual_sequencer [rv_dm_stress_all_vseq] m_mode_sequencer not configured. 1 test run
rv_dm_stress_all_with_rand_reset 44799060613296031262830454847904955611096169117583667260037819904684184629829 90
UVM_INFO @ 61306645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_base_vseq.sv:139) virtual_sequencer [rv_dm_common_vseq] m_mode_sequencer not configured. 1 test run
rv_dm_csr_mem_rw_with_rand_reset 102680924083572931503032200546162381896431756199884750363329372622299518422310 90
UVM_INFO @ 93294262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---