Simulation Results: spi_device/1r1w

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 86.26 %
  • code
  • 89.51 %
  • assert
  • 95.40 %
  • func
  • 73.86 %
  • block
  • 98.33 %
  • line
  • 98.75 %
  • branch
  • 96.96 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 297.000s 20121.260us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 35.651us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 306.369us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 17.000s 2481.086us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 4.000s 411.173us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 4.000s 432.801us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 306.369us 1 1 100.00
spi_device_csr_aliasing 4.000s 411.173us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 13.387us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 99.316us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 55.496us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 5.198us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 6.848us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 3.000s 40.598us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 3.000s 40.598us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 9.000s 1567.052us 1 1 100.00
spi_device_tpm_sts_read 3.000s 94.170us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 8.000s 970.952us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 87.000s 15565.770us 1 1 100.00
spi_device_flash_all 207.000s 17750.965us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 13.000s 5867.721us 1 1 100.00
spi_device_flash_all 207.000s 17750.965us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 13.000s 5867.721us 1 1 100.00
spi_device_flash_all 207.000s 17750.965us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 207.000s 17750.965us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 24.000s 1128.831us 1 1 100.00
spi_device_flash_all 207.000s 17750.965us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 24.000s 1128.831us 1 1 100.00
spi_device_flash_all 207.000s 17750.965us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 24.000s 1128.831us 1 1 100.00
spi_device_flash_all 207.000s 17750.965us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 24.000s 1128.831us 1 1 100.00
spi_device_flash_all 207.000s 17750.965us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 24.000s 1128.831us 1 1 100.00
spi_device_flash_all 207.000s 17750.965us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 19.000s 1974.227us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 44.000s 5979.797us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 44.000s 5979.797us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 44.000s 5979.797us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 5.000s 264.718us 1 1 100.00
spi_device_read_buffer_direct 19.000s 4032.689us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 44.000s 5979.797us 1 1 100.00
spi_device_flash_all 207.000s 17750.965us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 207.000s 17750.965us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 207.000s 17750.965us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.000s 37.897us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.000s 37.897us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 58.000s 3037.352us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 297.000s 20121.260us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 76.000s 3851.430us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 143.000s 4586.939us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 12.270us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 12.244us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.000s 50.276us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.000s 50.276us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 35.651us 1 1 100.00
spi_device_csr_rw 3.000s 306.369us 1 1 100.00
spi_device_csr_aliasing 4.000s 411.173us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 58.459us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 35.651us 1 1 100.00
spi_device_csr_rw 3.000s 306.369us 1 1 100.00
spi_device_csr_aliasing 4.000s 411.173us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 58.459us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 3.000s 270.383us 1 1 100.00
spi_device_tl_intg_err 26.000s 11885.125us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 26.000s 11885.125us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 55751803619058149443707840484620648169190787520022427615831719180809410679581 87
UVM_ERROR @ 4438463 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[994] not found within the scope .
UVM_ERROR @ 4438463 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[994] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 30841089551490429237251757776771461535632833838637635648950687876645408993753 85
UVM_ERROR @ 4460522 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3a9 [1110101001] vs 0x0 [0])
UVM_ERROR @ 4513522 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x25b [1001011011] vs 0x0 [0])
UVM_ERROR @ 4522522 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe9 [11101001] vs 0x0 [0])
UVM_ERROR @ 4555522 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2b5 [1010110101] vs 0x0 [0])