Simulation Results: clkmgr

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.57 %
  • code
  • 69.21 %
  • assert
  • 89.46 %
  • func
  • 65.04 %
  • line
  • 82.27 %
  • branch
  • 87.53 %
  • cond
  • 77.56 %
  • toggle
  • 98.68 %
  • FSM
  • 0.00 %
Validation stages
V1
83.33%
V2
69.23%
V2S
50.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.610s 36.183us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.880s 23.360us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.150s 53.066us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 2.960s 170.024us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.880s 15.835us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.170s 28.037us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.150s 53.066us 1 1 100.00
clkmgr_csr_aliasing 0.880s 15.835us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.580s 43.387us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.220s 26.211us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.900s 13.352us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.610s 36.183us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.830s 6.531us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.960s 5.844us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.830s 6.531us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.770s 4.487us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.000s 27.866us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.820s 36.945us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.820s 36.945us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
clkmgr_csr_hw_reset 0.880s 23.360us 1 1 100.00
clkmgr_csr_rw 1.150s 53.066us 1 1 100.00
clkmgr_csr_aliasing 0.880s 15.835us 1 1 100.00
clkmgr_same_csr_outstanding 1.020s 9.810us 0 1 0.00
tl_d_partial_access 3 4 75.00
clkmgr_csr_hw_reset 0.880s 23.360us 1 1 100.00
clkmgr_csr_rw 1.150s 53.066us 1 1 100.00
clkmgr_csr_aliasing 0.880s 15.835us 1 1 100.00
clkmgr_same_csr_outstanding 1.020s 9.810us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 6.150s 486.198us 1 1 100.00
clkmgr_tl_intg_err 0.990s 8.490us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.640s 106.322us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.640s 106.322us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.640s 106.322us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.640s 106.322us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.930s 7.134us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.990s 8.490us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.830s 6.531us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.960s 5.844us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.640s 106.322us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 2.820s 121.564us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.150s 53.066us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 6.150s 486.198us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.150s 53.066us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.150s 53.066us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 6.150s 486.198us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.800s 8.588us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 4.480s 128.880us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency_timeout 68035471412462149541509148011243641280882572820962164007553283528233202251565 84
UVM_INFO @ 5844440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 5078796681122752706805699519216413575511063276358738000080471208065734351127 245
UVM_INFO @ 128879745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 39802786765680851056672749676241368139996409589626865791110507235637868605005 84
UVM_INFO @ 4487399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 94658793503874222837628505399979015065405166488228797605741075179840640826213 81
UVM_INFO @ 7133881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 81712075620112925827870925813035406321090210189873133195907702147951530085136 84
UVM_INFO @ 8490383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency 102183570157248671382411324481421267257406465765249302468256805167328146264140 82
UVM_INFO @ 6531293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 114079736503708447176114825445548167524765359913473840646281046897935066219232 80
UVM_INFO @ 8587913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 48162524725528298728986390705442645354326423526454918960153044842742229563160 81
UVM_INFO @ 170024129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 8687529467281335164569024871508671396136579305162666824472182234360673729230 81
UVM_INFO @ 9810007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---