Simulation Results: dma

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 83.41 %
  • code
  • 90.72 %
  • assert
  • 95.44 %
  • func
  • 64.07 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.31 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 1191.382us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 1129.012us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 6.000s 619.189us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 62.764us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 36.088us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 6.000s 903.611us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 2.000s 52.132us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 29.361us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 36.088us 1 1 100.00
dma_csr_aliasing 2.000s 52.132us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 91.000s 4962.840us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 413.000s 315386.008us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 401.000s 174428.256us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 401.000s 174428.256us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 413.000s 315386.008us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 1155.000s 953663.465us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 401.000s 174428.256us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 6.000s 441.642us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 244.000s 70564.642us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 32.258us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 114.650us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 89.276us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 89.276us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 62.764us 1 1 100.00
dma_csr_rw 2.000s 36.088us 1 1 100.00
dma_csr_aliasing 2.000s 52.132us 1 1 100.00
dma_same_csr_outstanding 2.000s 22.801us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 62.764us 1 1 100.00
dma_csr_rw 2.000s 36.088us 1 1 100.00
dma_csr_aliasing 2.000s 52.132us 1 1 100.00
dma_same_csr_outstanding 2.000s 22.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 16.000s 635.865us 1 1 100.00
dma_generic_stress 1155.000s 953663.465us 1 1 100.00
dma_handshake_stress 401.000s 174428.256us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 8.000s 3600.590us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 126.476us 1 1 100.00
dma_sec_cm 2.000s 10.671us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 179.000s 14970.441us 1 1 100.00
dma_longer_transfer 5.000s 232.585us 1 1 100.00
dma_stress_all_with_rand_reset 27.000s 963.079us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 108310221547627078326110124465076566738143136719302471805934098408532849821608 141
UVM_INFO @ 963079105ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---