Simulation Results: rv_dm/use_dmi_interface

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 86.27 %
  • code
  • 73.54 %
  • assert
  • 96.66 %
  • func
  • 88.62 %
  • block
  • 89.19 %
  • line
  • 89.01 %
  • branch
  • 70.64 %
  • toggle
  • 72.02 %
  • FSM
  • 62.50 %
Validation stages
V1
88.89%
V2
60.87%
V2S
85.71%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 41.000s 611.340us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 40.000s 209.206us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 35.000s 164.990us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 50.000s 7159.572us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 38.000s 130.286us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 36.000s 7776.037us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 36.000s 1541.682us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 46.000s 6960.126us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 38.000s 7916.501us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 43.000s 648.505us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 37.000s 562.287us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 43.000s 222.486us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 38.000s 63.413us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 40.000s 294.309us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 42.000s 466.068us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 41.000s 207.662us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 39.000s 1018.759us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 43.000s 648.505us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 46.000s 175.529us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 39.000s 192.872us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 43.000s 222.486us 1 1 100.00
rom_read_access 0 1 0.00
rv_dm_rom_read_access 40.000s 91.073us 0 1 0.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 43.000s 1216.166us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 37.000s 865.455us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 63.000s 2185.379us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 48.000s 2191.591us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
rv_dm_csr_mem_rw_with_rand_reset 42.000s 43.995us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 48.000s 2191.591us 1 1 100.00
rv_dm_csr_rw 37.000s 865.455us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 45.000s 58.389us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 41.000s 30.560us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 41.000s 611.340us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 38.000s 314.998us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 38.000s 402.554us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 38.000s 113.001us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 39.000s 500.405us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 53.000s 7140.996us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 36.000s 86.075us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 45.000s 2634.803us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 46.000s 5513.872us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 34.000s 317.298us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 48.000s 4430.495us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 38.000s 185.815us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 39.000s 85.149us 0 1 0.00
tap_ctrl_transitions 0 2 0.00
rv_dm_tap_fsm 41.000s 43.622us 0 1 0.00
rv_dm_tap_fsm_rand_reset 48.000s 35.127us 0 1 0.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 33.000s 286.440us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 46.000s 1436.459us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 42.000s 47.109us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 46.000s 338.394us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 46.000s 338.394us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 48.000s 2191.591us 1 1 100.00
rv_dm_csr_hw_reset 43.000s 1216.166us 1 1 100.00
rv_dm_csr_rw 37.000s 865.455us 1 1 100.00
rv_dm_same_csr_outstanding 45.000s 327.948us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 48.000s 2191.591us 1 1 100.00
rv_dm_csr_hw_reset 43.000s 1216.166us 1 1 100.00
rv_dm_csr_rw 37.000s 865.455us 1 1 100.00
rv_dm_same_csr_outstanding 45.000s 327.948us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 39.000s 1739.818us 1 1 100.00
rv_dm_tl_intg_err 40.000s 670.013us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 40.000s 670.013us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 48.000s 4430.495us 1 1 100.00
rv_dm_debug_disabled 39.000s 104.909us 0 1 0.00
sec_cm_lc_dft_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 48.000s 4430.495us 1 1 100.00
rv_dm_debug_disabled 39.000s 104.909us 0 1 0.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 41.000s 611.340us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 43.000s 372.466us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 39.000s 64.080us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 39.000s 64.080us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 43.000s 372.466us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 37.000s 32.243us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 425.000s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:487) [scoreboard] sba_tl_access_q item uncompared: 2 test runs
rv_dm_sba_tl_access 73861913120291221529756637057486432481103523580685819758010149748350135197900 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @24884
rv_dm_autoincr_sba_tl_access 14812545738214596971022673216057186079590376570290026613595138043172239993667 132
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @25423
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp 2 test runs
rv_dm_delayed_resp_sba_tl_access 20077348183707193864069872115965436371045007660660382866908506339921607211592 107
UVM_INFO @ 86075485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 81854993309660787279694372585371978160172936051734775997488982989451667077021 119
UVM_INFO @ 2634803372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*]) 2 test runs
rv_dm_mem_tl_access_resuming 47137884349272785610081995861392166669902562886628940794216854932351203142100 87
UVM_INFO @ 63413463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 60838105003684513564570636697853905084478741379167343553876299291487827739837 90
UVM_INFO @ 1436458533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_base_vseq.sv:139) virtual_sequencer [seq] m_mode_sequencer not configured. 1 test run
rv_dm_tap_fsm 66494926668071268170271545160486428367491799735152174217120508532899495230967 88
UVM_INFO @ 43621637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_base_vseq.sv:139) virtual_sequencer [rv_dm_tap_fsm_vseq] m_mode_sequencer not configured. 1 test run
rv_dm_tap_fsm_rand_reset 78079177635725857537420837931938946465818374383342212094545769383150540949870 90
UVM_INFO @ 35126925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*]) 1 test run
rv_dm_hart_unavail 8738611611390979998818584237277841870610628318402529508605873899607104230294 87
UVM_INFO @ 85148598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) 1 test run
rv_dm_jtag_dmi_debug_disabled 44697674136041422596415137762166999923583420410737911116297028692203001584930 87
UVM_INFO @ 317297691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:415) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=*, but it was *"}. Item: (req: (cip_tl_seq_item@24941) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } 1 test run
rv_dm_rom_read_access 62292728071903226724969801117028784681071227771920279653347908121460611086126 87
).
UVM_INFO @ 91073201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_rv_dm_sva_*/rv_dm_enable_checker.sv,47): Assertion MemTLResponseWithoutDebugIsError_A has failed 1 test run
rv_dm_debug_disabled 76816910168180387889911107749972059694885534739505510375366244756031470830560 90
UVM_ERROR @ 104908845 ps: (rv_dm_enable_checker.sv:47) [ASSERT FAILED] MemTLResponseWithoutDebugIsError_A
UVM_INFO @ 104908845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rv_dm_scanmode 78254592785807048321952815746368187898995120467453471907574584292913126733817 87
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_base_vseq.sv:139) virtual_sequencer [rv_dm_stress_all_vseq] m_mode_sequencer not configured. 1 test run
rv_dm_stress_all_with_rand_reset 25619529101485758203282500184098343373016311811441200840874140829654426639738 90
UVM_INFO @ 32243176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_base_vseq.sv:139) virtual_sequencer [rv_dm_common_vseq] m_mode_sequencer not configured. 1 test run
rv_dm_csr_mem_rw_with_rand_reset 9722787386536182826524770659195777920424147353977951148234729753418196536493 90
UVM_INFO @ 43994900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---