Simulation Results: spi_device/1r1w

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.09 %
  • code
  • 89.49 %
  • assert
  • 95.40 %
  • func
  • 67.39 %
  • block
  • 98.35 %
  • line
  • 98.77 %
  • branch
  • 97.01 %
  • toggle
  • 72.61 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 118.000s 8739.643us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 34.735us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 72.089us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 12.000s 267.566us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 2.000s 87.816us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.000s 48.601us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 72.089us 1 1 100.00
spi_device_csr_aliasing 2.000s 87.816us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 34.406us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 59.120us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.000s 71.781us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 1.523us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 4.787us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 4.000s 44.296us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 4.000s 44.296us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 11.000s 2891.206us 1 1 100.00
spi_device_tpm_sts_read 2.000s 57.669us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 9.000s 1097.656us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 11.000s 4199.109us 1 1 100.00
spi_device_flash_all 316.000s 54531.723us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 11.000s 876.610us 1 1 100.00
spi_device_flash_all 316.000s 54531.723us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 11.000s 876.610us 1 1 100.00
spi_device_flash_all 316.000s 54531.723us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 316.000s 54531.723us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 7.000s 553.645us 1 1 100.00
spi_device_flash_all 316.000s 54531.723us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 7.000s 553.645us 1 1 100.00
spi_device_flash_all 316.000s 54531.723us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 7.000s 553.645us 1 1 100.00
spi_device_flash_all 316.000s 54531.723us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 7.000s 553.645us 1 1 100.00
spi_device_flash_all 316.000s 54531.723us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 7.000s 553.645us 1 1 100.00
spi_device_flash_all 316.000s 54531.723us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.000s 176.449us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 72.000s 12290.553us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 72.000s 12290.553us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 72.000s 12290.553us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 7.000s 222.847us 1 1 100.00
spi_device_read_buffer_direct 11.000s 3381.783us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 72.000s 12290.553us 1 1 100.00
spi_device_flash_all 316.000s 54531.723us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 316.000s 54531.723us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 316.000s 54531.723us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.000s 243.456us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.000s 243.456us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 81.000s 3429.530us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 118.000s 8739.643us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 540.000s 68354.842us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 856.000s 106224.490us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 32.738us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 17.408us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.000s 383.964us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.000s 383.964us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 34.735us 1 1 100.00
spi_device_csr_rw 3.000s 72.089us 1 1 100.00
spi_device_csr_aliasing 2.000s 87.816us 1 1 100.00
spi_device_same_csr_outstanding 6.000s 246.975us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 34.735us 1 1 100.00
spi_device_csr_rw 3.000s 72.089us 1 1 100.00
spi_device_csr_aliasing 2.000s 87.816us 1 1 100.00
spi_device_same_csr_outstanding 6.000s 246.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 4.000s 1533.099us 1 1 100.00
spi_device_tl_intg_err 29.000s 6283.307us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 29.000s 6283.307us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 5920607405855186944914104999179826986747945662399692595278449355160884936842 87
UVM_ERROR @ 1186437 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[984] not found within the scope .
UVM_ERROR @ 1186437 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[984] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 98925836399025540986773357337684622769716983802512681219907263484851788387992 85
UVM_ERROR @ 2423959 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x59 [1011001] vs 0x0 [0])
UVM_ERROR @ 2432959 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb0 [10110000] vs 0x0 [0])
UVM_ERROR @ 2499959 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5b [1011011] vs 0x0 [0])
UVM_ERROR @ 2509959 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3f5 [1111110101] vs 0x0 [0])