Simulation Results: uart

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.17 %
  • code
  • 73.69 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 98.66 %
  • line
  • 99.24 %
  • branch
  • 97.42 %
  • toggle
  • 73.08 %
  • FSM
  • 25.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 5.000s 698.695us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 37.651us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 16.177us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 182.404us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 2.000s 49.188us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 2.000s 17.437us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 16.177us 1 1 100.00
uart_csr_aliasing 2.000s 49.188us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 152.000s 64937.942us 1 1 100.00
parity 2 2 100.00
uart_smoke 5.000s 698.695us 1 1 100.00
uart_tx_rx 152.000s 64937.942us 1 1 100.00
parity_error 2 2 100.00
uart_intr 12.000s 49207.710us 1 1 100.00
uart_rx_parity_err 127.000s 197902.469us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 152.000s 64937.942us 1 1 100.00
uart_intr 12.000s 49207.710us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 36.000s 119391.294us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 44.000s 20737.981us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 39.000s 82743.251us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 12.000s 49207.710us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 12.000s 49207.710us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 12.000s 49207.710us 1 1 100.00
perf 1 1 100.00
uart_perf 38.000s 5787.787us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 28.000s 7278.539us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 28.000s 7278.539us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 34.000s 19335.339us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 31.000s 32920.436us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 3.000s 634.511us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 4.000s 1376.773us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 285.000s 201972.566us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 1553.000s 218567.299us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 1.000s 56.534us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 18.509us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 3.000s 40.165us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 3.000s 40.165us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 37.651us 1 1 100.00
uart_csr_rw 1.000s 16.177us 1 1 100.00
uart_csr_aliasing 2.000s 49.188us 1 1 100.00
uart_same_csr_outstanding 2.000s 31.407us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 37.651us 1 1 100.00
uart_csr_rw 1.000s 16.177us 1 1 100.00
uart_csr_aliasing 2.000s 49.188us 1 1 100.00
uart_same_csr_outstanding 2.000s 31.407us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 68.452us 1 1 100.00
uart_tl_intg_err 2.000s 188.057us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 188.057us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 53.000s 3203.997us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:376) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_noise_filter 27710916615159210676271392159091045421357792473932078046496921003102740671572 86
UVM_ERROR @ 19289672002 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 19294550785 ps: (uart_scoreboard.sv:376) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 19294550785 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 19295500279 ps: (uart_scoreboard.sv:376) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR (uart_scoreboard.sv:499) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_stress_all 82947399899166696473230426750348464170927953319878511821191886954553911060230 145
UVM_ERROR @ 217258975544 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 217258985961 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (19 [0x13] vs 239 [0xef]) reg name: uart_reg_block.rdata
UVM_ERROR @ 217448304519 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 217448325353 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty