TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Tuesday April 01 2025 20:13:39 UTC

GitHub Revision: ae78b92590

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 24 25 96.00
AES/UNMASKED 28 32 87.50
AES/MASKED 28 32 87.50
AON_TIMER 23 23 100.00
CSRNG 18 19 94.74
EDN 20 21 95.24
ENTROPY_SRC 17 22 77.27
HMAC 28 28 100.00
I2C 46 50 92.00
KEYMGR 26 30 86.67
KMAC/MASKED 36 40 90.00
KMAC/UNMASKED 36 40 90.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 38 39 97.44
LC_CTRL/VOLATILE_UNLOCK_ENABLED 38 39 97.44
OTBN 41 41 100.00
PATTGEN 17 18 94.44
PRIM_ALERT 4 4 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 19 19 100.00
ROM_CTRL/64KB 19 19 100.00
RV_DM/USE_JTAG_INTERFACE 44 53 83.02
RV_TIMER 15 16 93.75
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SPI_DEVICE/2P 32 33 96.97
SRAM_CTRL/MAIN 30 31 96.77
SRAM_CTRL/RET 30 31 96.77
SYSRST_CTRL 27 27 100.00
UART 27 27 100.00
USBDEV 97 99 97.98
GPIO 26 27 96.30
ALERT_HANDLER 21 26 80.77
CLKMGR 25 27 92.59
FLASH_CTRL 54 78 69.23
OTP_CTRL 24 30 80.00
PWM 8 17 47.06
PWRMGR 27 29 93.10
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
CHIP 245 325 75.38