Simulation Results: i2c

 
11/03/2026 18:08:48 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.07 %
  • code
  • 81.02 %
  • assert
  • 95.98 %
  • func
  • 78.22 %
  • line
  • 96.29 %
  • branch
  • 91.98 %
  • cond
  • 84.52 %
  • toggle
  • 89.45 %
  • FSM
  • 42.86 %
Validation stages
V1
100.00%
V2
89.80%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 12.900s 0.000us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 19.620s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.890s 0.000us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.910s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.510s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.180s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.090s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.910s 0.000us 1 1 100.00
i2c_csr_aliasing 1.180s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.040s 0.000us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 5.160s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 27.300s 0.000us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.790s 0.000us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 47.560s 0.000us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 57.150s 0.000us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.930s 0.000us 1 1 100.00
i2c_host_fifo_fmt_empty 3.030s 0.000us 1 1 100.00
i2c_host_fifo_reset_rx 3.680s 0.000us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 34.060s 0.000us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 23.260s 0.000us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 1.070s 0.000us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 3.650s 0.000us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 25.320s 0.000us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.620s 0.000us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 4.900s 0.000us 1 1 100.00
i2c_target_intr_smoke 4.690s 0.000us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.120s 0.000us 1 1 100.00
i2c_target_fifo_reset_tx 1.780s 0.000us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 22.320s 0.000us 1 1 100.00
i2c_target_stress_rd 4.900s 0.000us 1 1 100.00
i2c_target_intr_stress_wr 363.440s 0.000us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 5.110s 0.000us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 2.080s 0.000us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.330s 0.000us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 2.260s 0.000us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.790s 0.000us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.120s 0.000us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 27.300s 0.000us 1 1 100.00
i2c_host_perf_precise 0.970s 0.000us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 23.260s 0.000us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 1.680s 0.000us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 1.790s 0.000us 1 1 100.00
i2c_target_nack_acqfull_addr 1.650s 0.000us 1 1 100.00
i2c_target_nack_txstretch 1.250s 0.000us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 7.420s 0.000us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.700s 0.000us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.600s 0.000us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.810s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.080s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.080s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.890s 0.000us 1 1 100.00
i2c_csr_rw 0.910s 0.000us 1 1 100.00
i2c_csr_aliasing 1.180s 0.000us 1 1 100.00
i2c_same_csr_outstanding 1.040s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.890s 0.000us 1 1 100.00
i2c_csr_rw 0.910s 0.000us 1 1 100.00
i2c_csr_aliasing 1.180s 0.000us 1 1 100.00
i2c_same_csr_outstanding 1.040s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.670s 0.000us 1 1 100.00
i2c_sec_cm 0.980s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.670s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 10.130s 0.000us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.010s 0.000us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 13.670s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 93623083679619733245538380983175862048915923934771514103588220004782591036177 94
UVM_ERROR @ 28692433 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 28692433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 67724624388760873352135418874093566723132424005229151468895603122522156092594 146
UVM_ERROR @ 4124844128 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 4124844128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 14264830746671444652193828528099755669808156229535051287030461866727317374990 84
UVM_ERROR @ 1185882848 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 1185882848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*])
i2c_target_unexp_stop 64836140294887788698579809564217928164634588834381749634884292005405936517378 78
UVM_ERROR @ 15158122 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 15158122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 55800550208640033445463948977174167385737189030278881821183771214961640770176 101
UVM_ERROR @ 637057145 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 637057145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 63288214253911866910047938527328240995684313801482938538386552898536702936358 90
UVM_ERROR @ 6291776038 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6291776038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
i2c_host_mode_toggle 85005173295779225237008133235938762306032700800804482261276686546848288930553 87
UVM_ERROR @ 67333865 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: *
i2c_target_nack_txstretch 69182723927036958835345058651183262129741054562792098123720623185133964136411 78
UVM_ERROR @ 776914423 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 776914423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---