Simulation Results: pattgen

 
12/03/2026 17:23:11 DVSim: v1.14.2 sha: bbf86e0 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.41 %
  • code
  • 98.14 %
  • assert
  • 96.95 %
  • func
  • 88.15 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 94.43 %
Validation stages
V1
100.00%
V2
93.75%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 2.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 2.000s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 0.000us 1 1 100.00
pattgen_csr_aliasing 2.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 13.000s 0.000us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 8.000s 0.000us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 0.000us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 0.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 0.000us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 0.000us 1 1 100.00
pattgen_csr_rw 1.000s 0.000us 1 1 100.00
pattgen_csr_aliasing 2.000s 0.000us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 0.000us 1 1 100.00
pattgen_csr_rw 1.000s 0.000us 1 1 100.00
pattgen_csr_aliasing 2.000s 0.000us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 2.000s 0.000us 1 1 100.00
pattgen_sec_cm 2.000s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 86.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
pattgen_inactive_level 19.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6)
pattgen_inactive_level 59630122109133380034065722841283061685296573318004073624475310339239494047502 99
UVM_FATAL @ 10014608941 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xd988ac10, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
UVM_INFO @ 10014608941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 12834006251706144459085274067164093220396924109573252276690694220842321473638 165
UVM_ERROR @ 815481512 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 815490687 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 815490687 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 815541707 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Job timed out after * minutes
pattgen_stress_all 17820306631001676958297886564110680816428606815690386516766992273808905200142 None
Job timed out after 180 minutes