Simulation Results: i2c

 
19/03/2026 20:49:13 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.25 %
  • code
  • 81.45 %
  • assert
  • 96.19 %
  • func
  • 78.12 %
  • line
  • 96.41 %
  • branch
  • 92.41 %
  • cond
  • 84.74 %
  • toggle
  • 89.66 %
  • FSM
  • 44.05 %
Validation stages
V1
100.00%
V2
89.80%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 21.200s 0.000us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 9.010s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.760s 0.000us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.790s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.610s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.930s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.790s 0.000us 1 1 100.00
i2c_csr_aliasing 1.610s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 3.210s 0.000us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 55.950s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 174.480s 0.000us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.650s 0.000us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 59.000s 0.000us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 38.110s 0.000us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.950s 0.000us 1 1 100.00
i2c_host_fifo_fmt_empty 5.930s 0.000us 1 1 100.00
i2c_host_fifo_reset_rx 3.290s 0.000us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 74.820s 0.000us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 7.480s 0.000us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 1.470s 0.000us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 2.380s 0.000us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 782.000s 0.000us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.010s 0.000us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 19.400s 0.000us 1 1 100.00
i2c_target_intr_smoke 3.210s 0.000us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.100s 0.000us 1 1 100.00
i2c_target_fifo_reset_tx 1.120s 0.000us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 53.010s 0.000us 1 1 100.00
i2c_target_stress_rd 19.400s 0.000us 1 1 100.00
i2c_target_intr_stress_wr 18.310s 0.000us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.590s 0.000us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 27.880s 0.000us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 2.480s 0.000us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 10.000s 0.000us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.340s 0.000us 1 1 100.00
i2c_target_fifo_watermarks_tx 0.800s 0.000us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 174.480s 0.000us 1 1 100.00
i2c_host_perf_precise 21.960s 0.000us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 7.480s 0.000us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 1.950s 0.000us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 1.820s 0.000us 1 1 100.00
i2c_target_nack_acqfull_addr 2.000s 0.000us 1 1 100.00
i2c_target_nack_txstretch 1.110s 0.000us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 2.020s 0.000us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.770s 0.000us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.590s 0.000us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.710s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.290s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.290s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.760s 0.000us 1 1 100.00
i2c_csr_rw 0.790s 0.000us 1 1 100.00
i2c_csr_aliasing 1.610s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.990s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.760s 0.000us 1 1 100.00
i2c_csr_rw 0.790s 0.000us 1 1 100.00
i2c_csr_aliasing 1.610s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.990s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.310s 0.000us 1 1 100.00
i2c_sec_cm 0.800s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.310s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 21.120s 0.000us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.220s 0.000us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 4.940s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 113514472107620121522524017736062390385197089156729155934329733336537510310754 118
UVM_ERROR @ 807685295 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 807685295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 113988809692938684324114051911331107123033194084795395844410506603938227721740 118
UVM_ERROR @ 5643358277 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 5643358277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 51061241132964315750732349909504237436781126332396627888602964297573577981163 84
UVM_ERROR @ 3109088825 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 3109088825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])
i2c_target_unexp_stop 96151582209268529414922411476876002009208655486805405596256915996782191411805 78
UVM_ERROR @ 496393661 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 142 [0x8e])
UVM_INFO @ 496393661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 70129612755220626361587835478244207934215814119828761818435627870382465849297 79
UVM_FATAL @ 10029954724 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10029954724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 9136200536611902285224601226186579001591891742827204445145497172053367528926 101
UVM_ERROR @ 3489715071 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3489715071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 45341376339223826356606019805631249646231513723118539760770665204511609055736 84
UVM_ERROR @ 338880716 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 338880716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
i2c_host_mode_toggle 19218776202758144740617758278015689981201420373149794905678133860796366857962 87
UVM_ERROR @ 74240057 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
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