Simulation Results: i2c

 
26/03/2026 17:19:52 DVSim: v1.16.0 sha: dbdbe3d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.76 %
  • code
  • 80.64 %
  • assert
  • 95.98 %
  • func
  • 80.66 %
  • line
  • 95.92 %
  • branch
  • 91.55 %
  • cond
  • 84.59 %
  • toggle
  • 89.45 %
  • FSM
  • 41.67 %
Validation stages
V1
100.00%
V2
87.76%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 11.850s 0.000us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 19.810s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.740s 0.000us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.730s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 1.790s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.440s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.830s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.730s 0.000us 1 1 100.00
i2c_csr_aliasing 1.440s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.740s 0.000us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 0.880s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 62.770s 0.000us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.630s 0.000us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 51.760s 0.000us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 105.310s 0.000us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.830s 0.000us 1 1 100.00
i2c_host_fifo_fmt_empty 4.470s 0.000us 1 1 100.00
i2c_host_fifo_reset_rx 7.320s 0.000us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 122.180s 0.000us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 19.310s 0.000us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 1.160s 0.000us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.980s 0.000us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 234.000s 0.000us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 2.950s 0.000us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 8.040s 0.000us 1 1 100.00
i2c_target_intr_smoke 2.560s 0.000us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.000s 0.000us 1 1 100.00
i2c_target_fifo_reset_tx 1.270s 0.000us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 7.930s 0.000us 1 1 100.00
i2c_target_stress_rd 8.040s 0.000us 1 1 100.00
i2c_target_intr_stress_wr 295.990s 0.000us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.980s 0.000us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 130.770s 0.000us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 2.900s 0.000us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 5.170s 0.000us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.520s 0.000us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.300s 0.000us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 62.770s 0.000us 1 1 100.00
i2c_host_perf_precise 0.860s 0.000us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 19.310s 0.000us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 3.220s 0.000us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 1.860s 0.000us 1 1 100.00
i2c_target_nack_acqfull_addr 1.760s 0.000us 1 1 100.00
i2c_target_nack_txstretch 1.090s 0.000us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 3.990s 0.000us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.700s 0.000us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.680s 0.000us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.660s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.610s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.610s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.740s 0.000us 1 1 100.00
i2c_csr_rw 0.730s 0.000us 1 1 100.00
i2c_csr_aliasing 1.440s 0.000us 1 1 100.00
i2c_same_csr_outstanding 1.130s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.740s 0.000us 1 1 100.00
i2c_csr_rw 0.730s 0.000us 1 1 100.00
i2c_csr_aliasing 1.440s 0.000us 1 1 100.00
i2c_same_csr_outstanding 1.130s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_sec_cm 0.840s 0.000us 1 1 100.00
i2c_tl_intg_err 1.170s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.170s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 3.550s 0.000us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.150s 0.000us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 4.870s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 53107807651595624000549571730218417112348815566855639373623863650565197297626 94
UVM_ERROR @ 119685921 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 119685921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 14934797432059169602342007491350879852742145864131272547145215326332812297405 119
UVM_ERROR @ 135849470 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 135849470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 95955781490311662625299069319904349362238348764754101188838128439843108416457 84
UVM_ERROR @ 4280003483 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 4280003483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*])
i2c_target_unexp_stop 49761426141167419315031240365659126860845642439173171468590014827871336836724 78
UVM_ERROR @ 509931214 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 509931214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 61799027788278192280099883009733011340889267000941971085019487824872304708717 79
UVM_FATAL @ 10019944957 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10019944957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 29802543785726319013587690201498082123111410750035111223917143537973134158286 84
UVM_ERROR @ 1464829226 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1464829226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 3472690114481467741484096918762458402676890585385706509297812981671801590661 85
UVM_ERROR @ 1641720374 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1641720374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
i2c_host_mode_toggle 3413348378881387015503818234035056620542626820039105884988846731189387820141 85
UVM_ERROR @ 197961076 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @18199
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: *
i2c_target_nack_txstretch 71876706407441600761167431177366393328510270785889231747518560927356768444794 78
UVM_ERROR @ 159576358 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 159576358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---