Simulation Results: i2c

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.00 %
  • code
  • 81.00 %
  • assert
  • 95.98 %
  • func
  • 78.01 %
  • line
  • 96.32 %
  • branch
  • 91.98 %
  • cond
  • 84.59 %
  • toggle
  • 89.24 %
  • FSM
  • 42.86 %
Validation stages
V1
100.00%
V2
85.37%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 23.210s 2897.369us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 6.760s 1409.420us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.790s 76.275us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.780s 144.320us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.900s 2266.376us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 0.990s 87.488us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.870s 69.030us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.780s 144.320us 1 1 100.00
i2c_csr_aliasing 0.990s 87.488us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.020s 29.050us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 215.390s 9887.896us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 24.090s 3562.428us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.730s 146.149us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 57.040s 3383.432us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 87.380s 25476.817us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.200s 162.358us 1 1 100.00
i2c_host_fifo_fmt_empty 4.700s 1512.916us 1 1 100.00
i2c_host_fifo_reset_rx 5.410s 558.720us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 40.560s 2151.093us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 9.280s 2612.852us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 0.900s 185.143us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.810s 7944.882us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 31.930s 14962.098us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.790s 991.313us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 25.410s 751.850us 1 1 100.00
i2c_target_intr_smoke 4.340s 11128.321us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.280s 202.591us 1 1 100.00
i2c_target_fifo_reset_tx 1.100s 160.735us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 119.520s 32093.559us 1 1 100.00
i2c_target_stress_rd 25.410s 751.850us 1 1 100.00
i2c_target_intr_stress_wr 54.820s 29893.184us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.910s 5782.864us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 1.000s 1593.084us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 4.040s 1251.848us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 5.670s 10284.505us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.060s 509.131us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.130s 592.901us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 24.090s 3562.428us 1 1 100.00
i2c_host_perf_precise 1.290s 102.039us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 9.280s 2612.852us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 2.450s 149.508us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 2.840s 555.607us 1 1 100.00
i2c_target_nack_acqfull_addr 1.790s 453.009us 1 1 100.00
i2c_target_nack_txstretch 1.640s 824.115us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 19.380s 1409.345us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.770s 2713.728us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.600s 51.236us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.750s 17.478us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.450s 77.193us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.450s 77.193us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.790s 76.275us 1 1 100.00
i2c_csr_rw 0.780s 144.320us 1 1 100.00
i2c_csr_aliasing 0.990s 87.488us 1 1 100.00
i2c_same_csr_outstanding 0.920s 58.373us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.790s 76.275us 1 1 100.00
i2c_csr_rw 0.780s 144.320us 1 1 100.00
i2c_csr_aliasing 0.990s 87.488us 1 1 100.00
i2c_same_csr_outstanding 0.920s 58.373us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_sec_cm 1.020s 83.227us 1 1 100.00
i2c_tl_intg_err 1.720s 307.181us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.720s 307.181us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 17.760s 2523.861us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.030s 1672.970us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 12.160s 4365.671us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 44848810530846358631444828506414434564481048365190179665698759690697730900183 94
UVM_ERROR @ 29050030 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 29050030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 107867427999035505936708426109756067739349372972032317869882345354770069749020 109
UVM_ERROR @ 9887896427 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 9887896427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 18869023275194297804880941183621045773506488062396560640478790556384116300883 84
UVM_ERROR @ 7944881505 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 7944881505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])
i2c_target_unexp_stop 30576658185514659537738771171584753618744852977899387784372753408211721024712 78
UVM_ERROR @ 1672969886 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 218 [0xda])
UVM_INFO @ 1672969886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 81653236690571991724450377244414749563745232061512833525945132962472170436913 79
UVM_FATAL @ 10284505320 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10284505320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 6397524484166383081274877226433715208436338770864370474380957105751719440481 91
UVM_ERROR @ 2523860624 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2523860624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 73387180988101862043828698110106533172336863598119377813772469387793830630108 107
UVM_ERROR @ 4365671419 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4365671419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access
i2c_host_mode_toggle 79360534908753227386926955084813642445638615785591233701047544595884640978990 86
Error-[NOA] Null object access
src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: *
i2c_target_nack_txstretch 111613836173665740349738504791745882168325065377920192919384115713044688470872 78
UVM_ERROR @ 824114980 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 824114980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---