Simulation Results: otp_ctrl

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.82 %
  • code
  • 76.94 %
  • assert
  • 92.00 %
  • func
  • 70.52 %
  • line
  • 88.48 %
  • branch
  • 81.90 %
  • cond
  • 89.22 %
  • toggle
  • 80.83 %
  • FSM
  • 44.27 %
Validation stages
V1
100.00%
V2
90.00%
V2S
77.78%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.020s 782.457us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 7.830s 1070.629us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.200s 99.922us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.390s 45.816us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 2.920s 83.377us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.790s 456.227us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.750s 940.033us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.390s 45.816us 1 1 100.00
otp_ctrl_csr_aliasing 3.790s 456.227us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.140s 39.218us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.190s 39.281us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 16.210s 9922.523us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.480s 97.781us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 13.060s 2711.469us 1 1 100.00
otp_ctrl_check_fail 10.790s 449.550us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 9.600s 3841.467us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 16.350s 2252.600us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 16.860s 1516.017us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 14.830s 1257.397us 1 1 100.00
otp_ctrl_parallel_lc_esc 14.420s 572.023us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 19.580s 1399.745us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 30.150s 5283.286us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 3.490s 254.583us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 55.550s 19091.377us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.620s 85.598us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.910s 62.713us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.920s 377.799us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.920s 377.799us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.200s 99.922us 1 1 100.00
otp_ctrl_csr_rw 1.390s 45.816us 1 1 100.00
otp_ctrl_csr_aliasing 3.790s 456.227us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.340s 315.843us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.200s 99.922us 1 1 100.00
otp_ctrl_csr_rw 1.390s 45.816us 1 1 100.00
otp_ctrl_csr_aliasing 3.790s 456.227us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.340s 315.843us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_tl_intg_err 14.030s 1322.526us 1 1 100.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 14.030s 1322.526us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 7.830s 1070.629us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 7.830s 1070.629us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 14.420s 572.023us 1 1 100.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.420s 572.023us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.420s 572.023us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 14.420s 572.023us 1 1 100.00
otp_ctrl_macro_errs 30.150s 5283.286us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.420s 572.023us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 14.420s 572.023us 1 1 100.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 14.420s 572.023us 1 1 100.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.420s 572.023us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.420s 572.023us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 14.420s 572.023us 1 1 100.00
otp_ctrl_macro_errs 30.150s 5283.286us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.420s 572.023us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 14.420s 572.023us 1 1 100.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.480s 97.781us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 10.790s 449.550us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 16.350s 2252.600us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 16.350s 2252.600us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 16.350s 2252.600us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 16.350s 2252.600us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 16.350s 2252.600us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 7.830s 1070.629us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 16.350s 2252.600us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 7.830s 1070.629us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 124.810s 22670.215us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 9.600s 3841.467us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 7.830s 1070.629us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 7.830s 1070.629us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 30.150s 5283.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 10.430s 5954.095us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.220s 86.505us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 29247136312106349463057538454015646378918311955959848673719991846370466394921 6330
UVM_ERROR @ 449550193 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4096 [0x1000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 449550193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 81062778092359208900645050272338818823363307331573889529656515049022730919941 95
UVM_ERROR @ 86505377 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 86505377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_stress_all 36078619550347188887357804554781399178417936253691973847792959797359674714242 39925
UVM_ERROR @ 19091377059 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 19091377059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
otp_ctrl_sec_cm 73885447498188625688980756344386880223130780612682817574886747547693229554509 2558
UVM_ERROR @ 22670214502 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
UVM_INFO @ 22670214502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---