Simulation Results: pattgen

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 8.000s 23.714us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 14.113us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 28.783us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 886.387us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 16.803us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 2.000s 61.846us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 28.783us 1 1 100.00
pattgen_csr_aliasing 1.000s 16.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 1002.000s 45115.253us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 13.000s 10991.203us 1 1 100.00
error 1 1 100.00
pattgen_error 5.000s 32.695us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 2.000s 369.360us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 12.869us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 11.596us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 112.299us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 112.299us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 14.113us 1 1 100.00
pattgen_csr_rw 1.000s 28.783us 1 1 100.00
pattgen_csr_aliasing 1.000s 16.803us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 17.226us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 14.113us 1 1 100.00
pattgen_csr_rw 1.000s 28.783us 1 1 100.00
pattgen_csr_aliasing 1.000s 16.803us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 17.226us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 1.000s 442.885us 1 1 100.00
pattgen_tl_intg_err 2.000s 431.717us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 431.717us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 61.000s 11939.804us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 1.000s 26.174us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 50393365441694965908586643489084768442283869574588992115844158521178045808060 129
UVM_ERROR @ 1839290407 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1839301118 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1839301118 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1839491594 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:
pattgen_stress_all 107681542574019580334093096243051126038382746720926427280589386534095012946623 137
UVM_ERROR @ 369359734 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10328