Simulation Results

Simulation Results: i2c

07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.60 %

code
80.89 %

assert
95.98 %

func
79.92 %

line
95.95 %

branch
91.63 %

cond
84.93 %

toggle
89.66 %

FSM
42.26 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	47.510s	6711.473us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	29.030s	2837.419us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.810s	21.694us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.700s	65.192us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.040s	609.353us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.200s	38.016us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.810s	70.469us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.700s	65.192us	1	1	100.00
	i2c_csr_aliasing	1.200s	38.016us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.730s	76.054us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	1164.470s	45018.561us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	84.420s	26563.015us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.670s	373.902us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	82.260s	5432.454us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	45.000s	11088.910us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.270s	144.509us	1	1	100.00
	i2c_host_fifo_fmt_empty	8.120s	441.167us	1	1	100.00
	i2c_host_fifo_reset_rx	4.330s	626.036us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	84.800s	2325.786us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	8.020s	1827.561us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	1.140s	72.148us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.850s	1899.970us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	35.350s	18692.165us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.210s	1374.620us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	17.640s	31451.111us	1	1	100.00
	i2c_target_intr_smoke	3.170s	2887.368us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.980s	189.449us	1	1	100.00
	i2c_target_fifo_reset_tx	0.860s	452.330us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	8.010s	19913.763us	1	1	100.00
	i2c_target_stress_rd	17.640s	31451.111us	1	1	100.00
	i2c_target_intr_stress_wr	4.460s	4743.056us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.510s	1151.138us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	22.370s	3260.273us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.480s	3134.122us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.260s	539.222us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.210s	1299.376us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.750s	36.463us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	84.420s	26563.015us	1	1	100.00
	i2c_host_perf_precise	1.120s	97.528us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	8.020s	1827.561us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.630s	236.076us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	2.270s	2197.357us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.110s	1042.886us	1	1	100.00
	i2c_target_nack_txstretch	1.140s	186.753us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	3.450s	579.026us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.520s	429.429us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.650s	26.255us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.690s	102.117us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.940s	135.639us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.940s	135.639us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.810s	21.694us	1	1	100.00
	i2c_csr_rw	0.700s	65.192us	1	1	100.00
	i2c_csr_aliasing	1.200s	38.016us	1	1	100.00
	i2c_same_csr_outstanding	0.930s	21.074us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.810s	21.694us	1	1	100.00
	i2c_csr_rw	0.700s	65.192us	1	1	100.00
	i2c_csr_aliasing	1.200s	38.016us	1	1	100.00
	i2c_same_csr_outstanding	0.930s	21.074us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.580s	424.299us	1	1	100.00
	i2c_sec_cm	0.970s	156.578us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.580s	424.299us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	4.600s	1553.185us	1
target_error_intr				1
	i2c_target_unexp_stop	2.080s	1351.104us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	6.880s	2517.227us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	104377072536989455293193196303914679368851731561664887192656573720019566168541	94	UVM_ERROR @ 76053942 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 76053942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
	i2c_host_stress_all	18975534879955577799794868645300308602469559174078808175572692809988024150128	121	UVM_ERROR @ 45018561202 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared: ---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @7780806
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	70472559968530582219125364637699321299955067233599279538483308625239790532933	84	UVM_ERROR @ 1899970359 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between UVM_INFO @ 1899970359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])
	i2c_target_unexp_stop	15267831314105160988246784486917022685369170879233859677028511155940711638780	78	UVM_ERROR @ 1351103706 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 47 [0x2f]) UVM_INFO @ 1351103706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	21530060717641196239492096185192620938611150555087509276663283567795838306330	86	UVM_ERROR @ 1553184740 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1553184740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
	i2c_target_stress_all_with_rand_reset	54634016813573748674759049374449373394916652282222554326150720161175452286090	86	UVM_ERROR @ 2517226948 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. UVM_INFO @ 2517226948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:
	i2c_target_nack_txstretch	30328031266811023569869894132578298895350101999472543271881129679373085649886	78	UVM_ERROR @ 186753449 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0 UVM_INFO @ 186753449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---