Simulation Results

Simulation Results: spi_device/1r1w

07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
84.16 %

code
93.06 %

assert
94.64 %

func
64.78 %

line
99.04 %

branch
98.20 %

cond
95.35 %

toggle
83.36 %

FSM
89.36 %

Validation stages

V1		100.00%
V2		92.31%
V2S		100.00%
unmapped		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	spi_device_flash_and_tpm	193.320s	144308.204us	1	1	100.00
csr_hw_reset				1	1	100.00
	spi_device_csr_hw_reset	1.090s	37.719us	1	1	100.00
csr_rw				1	1	100.00
	spi_device_csr_rw	1.830s	70.589us	1	1	100.00
csr_bit_bash				1	1	100.00
	spi_device_csr_bit_bash	9.280s	2429.358us	1	1	100.00
csr_aliasing				1	1	100.00
	spi_device_csr_aliasing	5.460s	330.097us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	spi_device_csr_mem_rw_with_rand_reset	1.510s	95.606us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	spi_device_csr_rw	1.830s	70.589us	1	1	100.00
	spi_device_csr_aliasing	5.460s	330.097us	1	1	100.00
mem_walk				1	1	100.00
	spi_device_mem_walk	0.660s	12.611us	1	1	100.00
mem_partial_access				1	1	100.00
	spi_device_mem_partial_access	1.820s	211.097us	1	1	100.00

24/26 passed

92.31 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				1	1	100.00
	spi_device_csb_read	0.890s	62.477us	1	1	100.00
mem_parity				0	1	0.00
	spi_device_mem_parity	0.730s	2.942us	0	1	0.00
mem_cfg				0	1	0.00
	spi_device_ram_cfg	0.660s	5.286us	0	1	0.00
tpm_read				1	1	100.00
	spi_device_tpm_rw	1.400s	33.362us	1	1	100.00
tpm_write				1	1	100.00
	spi_device_tpm_rw	1.400s	33.362us	1	1	100.00
tpm_hw_reg				2	2	100.00
	spi_device_tpm_read_hw_reg	4.660s	2174.063us	1	1	100.00
	spi_device_tpm_sts_read	0.840s	42.086us	1	1	100.00
tpm_fully_random_case				1	1	100.00
	spi_device_tpm_all	8.140s	1800.489us	1	1	100.00
pass_cmd_filtering				2	2	100.00
	spi_device_pass_cmd_filtering	4.910s	1868.565us	1	1	100.00
	spi_device_flash_all	24.940s	6799.564us	1	1	100.00
pass_addr_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	11.110s	3271.439us	1	1	100.00
	spi_device_flash_all	24.940s	6799.564us	1	1	100.00
pass_payload_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	11.110s	3271.439us	1	1	100.00
	spi_device_flash_all	24.940s	6799.564us	1	1	100.00
cmd_info_slots				1	1	100.00
	spi_device_flash_all	24.940s	6799.564us	1	1	100.00
cmd_read_status				2	2	100.00
	spi_device_intercept	1.760s	131.044us	1	1	100.00
	spi_device_flash_all	24.940s	6799.564us	1	1	100.00
cmd_read_jedec				2	2	100.00
	spi_device_intercept	1.760s	131.044us	1	1	100.00
	spi_device_flash_all	24.940s	6799.564us	1	1	100.00
cmd_read_sfdp				2	2	100.00
	spi_device_intercept	1.760s	131.044us	1	1	100.00
	spi_device_flash_all	24.940s	6799.564us	1	1	100.00
cmd_fast_read				2	2	100.00
	spi_device_intercept	1.760s	131.044us	1	1	100.00
	spi_device_flash_all	24.940s	6799.564us	1	1	100.00
cmd_read_pipeline				2	2	100.00
	spi_device_intercept	1.760s	131.044us	1	1	100.00
	spi_device_flash_all	24.940s	6799.564us	1	1	100.00
flash_cmd_upload				1	1	100.00
	spi_device_upload	4.550s	1043.820us	1	1	100.00
mailbox_command				1	1	100.00
	spi_device_mailbox	3.410s	270.862us	1	1	100.00
mailbox_cross_outside_command				1	1	100.00
	spi_device_mailbox	3.410s	270.862us	1	1	100.00
mailbox_cross_inside_command				1	1	100.00
	spi_device_mailbox	3.410s	270.862us	1	1	100.00
cmd_read_buffer				2	2	100.00
	spi_device_flash_mode	1.800s	124.043us	1	1	100.00
	spi_device_read_buffer_direct	3.300s	1106.115us	1	1	100.00
cmd_dummy_cycle				2	2	100.00
	spi_device_mailbox	3.410s	270.862us	1	1	100.00
	spi_device_flash_all	24.940s	6799.564us	1	1	100.00
quad_spi				1	1	100.00
	spi_device_flash_all	24.940s	6799.564us	1	1	100.00
dual_spi				1	1	100.00
	spi_device_flash_all	24.940s	6799.564us	1	1	100.00
4b_3b_feature				1	1	100.00
	spi_device_cfg_cmd	10.160s	3208.841us	1	1	100.00
write_enable_disable				1	1	100.00
	spi_device_cfg_cmd	10.160s	3208.841us	1	1	100.00
TPM_with_flash_or_passthrough_mode				1	1	100.00
	spi_device_flash_and_tpm	193.320s	144308.204us	1	1	100.00
tpm_and_flash_trans_with_min_inactive_time				1	1	100.00
	spi_device_flash_and_tpm_min_idle	36.140s	16114.058us	1	1	100.00
stress_all				1	1	100.00
	spi_device_stress_all	0.940s	52.938us	1	1	100.00
alert_test				1	1	100.00
	spi_device_alert_test	0.680s	42.960us	1	1	100.00
intr_test				1	1	100.00
	spi_device_intr_test	0.720s	24.668us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	spi_device_tl_errors	1.720s	71.857us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	spi_device_tl_errors	1.720s	71.857us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	spi_device_csr_hw_reset	1.090s	37.719us	1	1	100.00
	spi_device_csr_rw	1.830s	70.589us	1	1	100.00
	spi_device_csr_aliasing	5.460s	330.097us	1	1	100.00
	spi_device_same_csr_outstanding	3.180s	651.396us	1	1	100.00
tl_d_partial_access				4	4	100.00
	spi_device_csr_hw_reset	1.090s	37.719us	1	1	100.00
	spi_device_csr_rw	1.830s	70.589us	1	1	100.00
	spi_device_csr_aliasing	5.460s	330.097us	1	1	100.00
	spi_device_same_csr_outstanding	3.180s	651.396us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	spi_device_tl_intg_err	10.480s	4290.299us	1	1	100.00
	spi_device_sec_cm	1.080s	232.082us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	spi_device_tl_intg_err	10.480s	4290.299us	1	1	100.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	spi_device_flash_mode_ignore_cmds	35.250s	16845.949us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
	spi_device_mem_parity	98946279181859837514110488345241868809092875107105890828149816287625875407956	76	UVM_ERROR @ 1942164 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[11]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name UVM_ERROR @ 1942164 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data)) UVM_ERROR @ 1942164 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[907]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [] vs [*])
	spi_device_ram_cfg	52729504028846817542086348864342676179090871760437550333316959177296997916497	76	UVM_ERROR @ 2916138 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcd1c2c [110011010001110000101100] vs 0x0 [0]) UVM_ERROR @ 2987138 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9bb83a [100110111011100000111010] vs 0x0 [0]) UVM_ERROR @ 3039138 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6820c0 [11010000010000011000000] vs 0x0 [0]) UVM_ERROR @ 3050138 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x77b423 [11101111011010000100011] vs 0x0 [0]) UVM_ERROR @ 3098138 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x614b36 [11000010100101100110110] vs 0x0 [0])