Simulation Results: pattgen

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
81.82%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 3.000s 351.690us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 19.269us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 14.361us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 200.804us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 78.683us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 2.000s 35.291us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 14.361us 1 1 100.00
pattgen_csr_aliasing 1.000s 78.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 789.000s 600000.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 31.000s 2592.277us 1 1 100.00
error 1 1 100.00
pattgen_error 2.000s 80.204us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 10127.000s 5379450.930us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 27.333us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 2.000s 14.157us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 135.941us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 135.941us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 19.269us 1 1 100.00
pattgen_csr_rw 1.000s 14.361us 1 1 100.00
pattgen_csr_aliasing 1.000s 78.683us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 24.926us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 19.269us 1 1 100.00
pattgen_csr_rw 1.000s 14.361us 1 1 100.00
pattgen_csr_aliasing 1.000s 78.683us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 24.926us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 1.000s 99.053us 1 1 100.00
pattgen_sec_cm 1.000s 43.851us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 99.053us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 34.000s 3467.246us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 1.000s 28.778us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
pattgen_perf 81996178029570387299774864567405779053047711543401771261789897214566630288795 99
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 39122759629214204463715454594059547494549888251391429737481976842840574589410 126
UVM_ERROR @ 921910228 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 921910228 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 921931062 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:
pattgen_stress_all 112395514183364437618686045634282173798990138824788869380552275535424420513113 139
-------------------------------------
Name Type Size Value
-------------------------------------
exp_item pattgen_item - @101120