Simulation Results: otp_ctrl

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.36 %
  • code
  • 75.22 %
  • assert
  • 93.92 %
  • func
  • 65.94 %
  • line
  • 88.53 %
  • branch
  • 82.98 %
  • cond
  • 89.69 %
  • toggle
  • 74.98 %
  • FSM
  • 39.93 %
Validation stages
V1
88.89%
V2
75.00%
V2S
66.67%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.880s 712.653us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 5.660s 409.584us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.540s 100.190us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.280s 41.067us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.420s 1972.641us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.960s 425.458us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.040s 26.586us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.280s 41.067us 1 1 100.00
otp_ctrl_csr_aliasing 2.960s 425.458us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.370s 76.959us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.540s 137.551us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.060s 1182.691us 1 1 100.00
init_fail 0 1 0.00
otp_ctrl_init_fail 3.160s 287.260us 0 1 0.00
partition_check 0 2 0.00
otp_ctrl_background_chks 14.680s 7148.592us 0 1 0.00
otp_ctrl_check_fail 4.110s 1422.341us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.340s 2014.582us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 10.770s 822.171us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 15.390s 1095.339us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 10.630s 583.782us 1 1 100.00
otp_ctrl_parallel_lc_esc 4.200s 283.605us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 13.810s 6218.583us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 1.470s 56.918us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 3.010s 151.605us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 23.830s 2824.292us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.340s 130.670us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.550s 93.128us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.710s 137.298us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.710s 137.298us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.540s 100.190us 1 1 100.00
otp_ctrl_csr_rw 1.280s 41.067us 1 1 100.00
otp_ctrl_csr_aliasing 2.960s 425.458us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.360s 76.364us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.540s 100.190us 1 1 100.00
otp_ctrl_csr_rw 1.280s 41.067us 1 1 100.00
otp_ctrl_csr_aliasing 2.960s 425.458us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.360s 76.364us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
otp_ctrl_tl_intg_err 14.200s 3316.419us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 14.200s 3316.419us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 5.660s 409.584us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 5.660s 409.584us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.200s 283.605us 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.200s 283.605us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.200s 283.605us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.200s 283.605us 1 1 100.00
otp_ctrl_macro_errs 1.470s 56.918us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.200s 283.605us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.200s 283.605us 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.200s 283.605us 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.200s 283.605us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.200s 283.605us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.200s 283.605us 1 1 100.00
otp_ctrl_macro_errs 1.470s 56.918us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.200s 283.605us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.200s 283.605us 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 3.160s 287.260us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 4.110s 1422.341us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 10.770s 822.171us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 10.770s 822.171us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 10.770s 822.171us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 10.770s 822.171us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 10.770s 822.171us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 5.660s 409.584us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 10.770s 822.171us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 5.660s 409.584us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.530s 22185.178us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.340s 2014.582us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 5.660s 409.584us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 5.660s 409.584us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 1.470s 56.918us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 13.410s 7259.803us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 42.210s 6029.467us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_init_fail 25067143721603779360343527182727924532314239335535379306806026362982548663835 2957
UVM_INFO @ 287259567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_background_chks 46858372863279762680818423886972541113190733727452770077606851492321302555917 13100
UVM_INFO @ 7148592353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 2312830092776687157324409530309771080456349132259343244598364557381565930695 33478
UVM_INFO @ 2824292140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 55158820236494466075047543059245979828619516957189009971416313004185111678271 3257
UVM_INFO @ 1422340612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 108786799807968179001108156173182510924152109072649747731970664929247969367232 151
UVM_INFO @ 56918112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 8004143849066228189882078887044737702936102225495584589446253471015489846740 16917
UVM_INFO @ 6029466750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_csr_mem_rw_with_rand_reset 58901680657379761744594859975489116780574784735573096395393164516819175808419 92
UVM_INFO @ 26585867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---