Simulation Results

Simulation Results: uart

27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
81.60 %

code
95.73 %

assert
97.12 %

func
51.95 %

line
99.17 %

branch
97.44 %

cond
94.98 %

toggle
91.32 %

Validation stages

V1		100.00%
V2		90.91%
V2S		100.00%
V3		0.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	2.220s	677.518us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.620s	56.080us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	0.600s	40.404us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	1.340s	123.492us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	0.760s	25.127us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	0.990s	24.698us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	0.600s	40.404us	1	1	100.00
	uart_csr_aliasing	0.760s	25.127us	1	1	100.00

20/22 passed

90.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	6.800s	14065.222us	1	1	100.00
parity				2	2	100.00
	uart_smoke	2.220s	677.518us	1	1	100.00
	uart_tx_rx	6.800s	14065.222us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	53.800s	33205.406us	1	1	100.00
	uart_rx_parity_err	41.940s	33961.834us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	6.800s	14065.222us	1	1	100.00
	uart_intr	53.800s	33205.406us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	39.150s	305654.700us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	62.550s	105140.386us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	27.190s	36569.015us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	53.800s	33205.406us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	53.800s	33205.406us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	53.800s	33205.406us	1	1	100.00
perf				1	1	100.00
	uart_perf	918.190s	32447.792us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	10.590s	7139.324us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	10.590s	7139.324us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	4.590s	3764.274us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	17.670s	51417.619us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	1.960s	1158.132us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	7.290s	2116.289us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	518.470s	109727.094us	1	1	100.00
stress_all				0	1	0.00
	uart_stress_all	414.000s	41632.896us	0	1	0.00
alert_test				1	1	100.00
	uart_alert_test	0.640s	32.997us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	0.620s	16.348us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	1.620s	252.191us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	1.620s	252.191us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	0.620s	56.080us	1	1	100.00
	uart_csr_rw	0.600s	40.404us	1	1	100.00
	uart_csr_aliasing	0.760s	25.127us	1	1	100.00
	uart_same_csr_outstanding	0.900s	67.609us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	0.620s	56.080us	1	1	100.00
	uart_csr_rw	0.600s	40.404us	1	1	100.00
	uart_csr_aliasing	0.760s	25.127us	1	1	100.00
	uart_same_csr_outstanding	0.900s	67.609us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	1.000s	665.441us	1	1	100.00
	uart_tl_intg_err	1.230s	54.602us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	1.230s	54.602us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	uart_stress_all_with_rand_reset	8.160s	1018.745us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: , clk_pulses:
	uart_noise_filter	29015310895193587136742267675309371221663825997563257303599886177826788153974	75	UVM_ERROR @ 2601994317 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 2602014317 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (57 [0x39] vs 190 [0xbe]) reg name: uart_reg_block.rdata UVM_ERROR @ 2602034317 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 2602054317 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (57 [0x39] vs 119 [0x77]) reg name: uart_reg_block.rdata
	uart_stress_all	81525881467075587582694779422529169901439365351746743186071328909443247257313	104	UVM_ERROR @ 40014115877 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 40014127505 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata UVM_ERROR @ 40195710353 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0 UVM_ERROR @ 40195721981 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [] vs [*]) Interrupt_pin: TxEmpty
	uart_stress_all_with_rand_reset	11473374652088507947683870047704317594476535943189643680278836795542969710576	89	UVM_INFO @ 66423210 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/605 UVM_INFO @ 169877652 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/605 UVM_INFO @ 272332095 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/605 UVM_INFO @ 340927986 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/605