Simulation Results

Simulation Results: i2c

25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
87.17 %

code
81.92 %

assert
96.83 %

func
82.77 %

line
96.48 %

branch
92.55 %

cond
87.07 %

toggle
89.45 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	48.570s	1547.274us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	8.320s	992.501us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.880s	21.836us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.730s	68.556us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.130s	217.944us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.640s	521.181us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	73.930us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.730s	68.556us	1	1	100.00
	i2c_csr_aliasing	1.640s	521.181us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				1	1	100.00
	i2c_host_error_intr	1.310s	76.772us	1	1	100.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	393.000s	50017.974us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	16.870s	20320.350us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.870s	29.025us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	54.750s	23337.991us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	117.150s	2579.886us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.100s	95.551us	1	1	100.00
	i2c_host_fifo_fmt_empty	6.300s	2149.093us	1	1	100.00
	i2c_host_fifo_reset_rx	7.440s	803.111us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	21.360s	7820.779us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	24.460s	862.841us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	4.450s	585.668us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.870s	2637.128us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	64.660s	167047.126us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.940s	526.683us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	5.640s	440.010us	1	1	100.00
	i2c_target_intr_smoke	6.670s	6477.049us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.260s	180.600us	1	1	100.00
	i2c_target_fifo_reset_tx	0.850s	156.266us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	51.710s	40649.028us	1	1	100.00
	i2c_target_stress_rd	5.640s	440.010us	1	1	100.00
	i2c_target_intr_stress_wr	9.290s	5744.729us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	5.390s	10233.698us	1	1	100.00
target_clock_stretch				0	1	0.00
	i2c_target_stretch	1.650s	10212.994us	0	1	0.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.850s	623.115us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	10.300s	10242.057us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.960s	1195.690us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.440s	146.805us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	16.870s	20320.350us	1	1	100.00
	i2c_host_perf_precise	769.020s	24419.816us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	24.460s	862.841us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.460s	119.990us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	2.480s	559.966us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.570s	684.969us	1	1	100.00
	i2c_target_nack_txstretch	1.690s	199.267us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	5.610s	194.098us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.680s	857.613us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.950s	34.457us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.680s	15.783us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.880s	77.365us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.880s	77.365us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.880s	21.836us	1	1	100.00
	i2c_csr_rw	0.730s	68.556us	1	1	100.00
	i2c_csr_aliasing	1.640s	521.181us	1	1	100.00
	i2c_same_csr_outstanding	0.970s	21.473us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.880s	21.836us	1	1	100.00
	i2c_csr_rw	0.730s	68.556us	1	1	100.00
	i2c_csr_aliasing	1.640s	521.181us	1	1	100.00
	i2c_same_csr_outstanding	0.970s	21.473us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.170s	263.772us	1	1	100.00
	i2c_sec_cm	0.840s	79.154us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.170s	263.772us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	20.850s	2872.583us	1
target_error_intr				1
	i2c_target_unexp_stop	0.880s	57.050us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	1.730s	27.084us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	34240976178189289644949403872837137905066193002161787459573675526996092804974	84	UVM_INFO @ 2637127878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!				1 test run
	i2c_target_stretch	15011658685984752974450125464158253027023633936688966378370397448334137433461	78	UVM_INFO @ 10212994380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	47981483350087493586227856989321078195233522606486106034007147665009167234220	78	UVM_INFO @ 57049673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	77815434659380616200929231855636434660563051334243869790414568749853173418705	79	UVM_INFO @ 10242057352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	44888724615218760912479328526927357406100939958436235869535199186498527021908	94	UVM_INFO @ 2872582612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_target_stress_all_with_rand_reset	81202237475781902110549425634556291240640372472938626035472768090879524357735	85	UVM_INFO @ 27084076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:				1 test run
	i2c_target_nack_txstretch	101300205758515693690737935679284669198162984913767945719132259735363551705770	78	UVM_INFO @ 199266741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---