Simulation Results: chip

 
26/05/2026 15:30:30 DVSim: v1.49.6 sha: cbf0611 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 77.62 %
  • code
  • 85.29 %
  • assert
  • 97.25 %
  • func
  • 50.33 %
  • line
  • 94.42 %
  • branch
  • 93.85 %
  • cond
  • 89.74 %
  • toggle
  • 91.29 %
  • FSM
  • 57.14 %
Validation stages
unmapped
76.90%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 253 329 76.90
chip_csr_bit_bash 332.260s 4467.454us 1 1 100.00
chip_csr_aliasing 5104.830s 35835.919us 1 1 100.00
chip_same_csr_outstanding 2616.100s 29673.931us 1 1 100.00
chip_sw_example_flash 104.040s 2733.764us 1 1 100.00
chip_sw_example_rom 65.770s 2376.778us 1 1 100.00
chip_sw_example_manufacturer 121.100s 2676.840us 1 1 100.00
chip_sw_example_concurrency 158.370s 2450.675us 1 1 100.00
chip_sival_flash_info_access 202.870s 3609.885us 1 1 100.00
chip_sw_all_escalation_resets 199.480s 3216.018us 0 1 0.00
chip_sw_rstmgr_rst_cnsty_escalation 19.650s 10.320us 0 1 0.00
chip_sw_data_integrity_escalation 428.530s 5481.317us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 208.180s 3319.297us 1 1 100.00
chip_sw_sleep_pin_wake 208.230s 3862.339us 1 1 100.00
chip_sw_sleep_pin_retention 198.020s 3260.458us 1 1 100.00
chip_sw_sleep_pwm_pulses 824.470s 8669.491us 1 1 100.00
chip_sw_pattgen_ios 139.150s 3328.133us 1 1 100.00
chip_sw_uart_tx_rx 361.940s 4570.900us 1 1 100.00
chip_sw_uart_tx_rx_idx1 394.090s 4943.228us 1 1 100.00
chip_sw_uart_tx_rx_idx2 425.810s 5027.920us 1 1 100.00
chip_sw_uart_tx_rx_idx3 349.040s 4136.414us 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7889.180s 63821.283us 1 1 100.00
chip_sw_usbdev_vbus 185.730s 2778.213us 1 1 100.00
chip_sw_usbdev_dpi 1881.220s 12163.496us 1 1 100.00
chip_sw_usbdev_pullup 163.440s 2906.543us 1 1 100.00
chip_sw_usbdev_aon_pullup 256.690s 3627.348us 1 1 100.00
chip_sw_usbdev_setuprx 314.750s 3576.587us 1 1 100.00
chip_sw_usbdev_config_host 1017.550s 8751.722us 1 1 100.00
chip_sw_usbdev_pincfg 5540.270s 31688.268us 1 1 100.00
chip_sw_usbdev_stream 2980.070s 18442.932us 1 1 100.00
chip_sw_usbdev_toggle_restore 168.680s 3184.364us 1 1 100.00
chip_sw_inject_scramble_seed 8055.640s 57851.270us 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7110.240s 55138.088us 1 1 100.00
chip_sw_uart_rand_baudrate 1097.820s 8534.363us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 313.730s 4024.838us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1054.420s 13705.332us 1 1 100.00
chip_sw_i2c_host_tx_rx 509.120s 5700.078us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 344.780s 4326.754us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 470.200s 5919.538us 1 1 100.00
chip_sw_i2c_device_tx_rx 292.980s 4318.442us 1 1 100.00
chip_sw_spi_device_tpm 218.320s 3730.747us 1 1 100.00
chip_sw_spi_host_tx_rx 143.820s 2329.921us 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 237.410s 4360.992us 1 1 100.00
chip_sw_spi_device_pass_through 263.520s 3782.196us 1 1 100.00
chip_sw_spi_device_pass_through_collision 226.090s 3566.542us 0 1 0.00
chip_sw_gpio 270.440s 3729.149us 1 1 100.00
chip_sw_flash_ctrl_ops 396.870s 4354.176us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 377.690s 4473.507us 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 137.340s 3279.309us 0 1 0.00
chip_sw_flash_ctrl_access 575.360s 5577.830us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 602.740s 5494.198us 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 246.410s 3466.201us 1 1 100.00
chip_sw_flash_init 1039.640s 22286.593us 1 1 100.00
chip_sw_flash_rma_unlocked 3673.660s 44397.805us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 566.760s 5571.846us 1 1 100.00
chip_sw_kmac_entropy 1161.570s 8307.753us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 201.400s 3431.759us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 203.150s 3624.257us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 679.880s 8821.631us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 474.340s 5054.184us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 411.100s 5278.721us 0 1 0.00
chip_sw_otp_ctrl_vendor_test_csr_access 126.740s 2358.373us 1 1 100.00
chip_sw_otp_ctrl_escalation 174.640s 3368.202us 0 1 0.00
chip_sw_otp_ctrl_dai_lock 887.870s 7610.893us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 5.540s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 176.990s 3332.812us 1 1 100.00
chip_sw_otp_ctrl_descrambling 249.740s 3483.323us 1 1 100.00
chip_sw_lc_ctrl_transition 377.530s 7781.528us 1 1 100.00
chip_sw_lc_ctrl_rma_to_scrap 127.540s 3278.703us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 91.930s 3827.332us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 82.780s 2782.188us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 102.470s 3566.559us 1 1 100.00
chip_sw_lc_walkthrough_dev 832.080s 26374.714us 0 1 0.00
chip_sw_lc_walkthrough_prod 620.570s 7616.633us 0 1 0.00
chip_sw_lc_walkthrough_prodend 533.520s 9317.101us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 919.260s 26888.532us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 63.180s 2318.261us 1 1 100.00
chip_sw_lc_walkthrough_rma 374.780s 7246.608us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 2053.020s 38872.525us 1 1 100.00
chip_sw_rstmgr_sw_req 299.680s 4726.059us 1 1 100.00
chip_sw_rstmgr_sw_rst 150.410s 2612.066us 1 1 100.00
chip_sw_rstmgr_alert_info 1369.220s 14432.955us 1 1 100.00
chip_sw_rstmgr_cpu_info 386.980s 6382.050us 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 67.990s 1874.793us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 239.930s 4806.272us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 726.020s 7869.065us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 892.490s 10785.472us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1656.950s 21466.166us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 202.120s 5735.440us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1015.200s 12425.514us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 373.680s 7158.071us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 370.230s 5567.274us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 143.720s 3101.165us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 425.910s 7889.943us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1392.620s 19948.344us 0 1 0.00
chip_sw_pwrmgr_sleep_disabled 136.250s 3012.347us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 305.310s 4374.212us 1 1 100.00
chip_sw_rv_timer_irq 177.640s 3620.904us 1 1 100.00
chip_sw_rv_timer_systick_test 5696.830s 38380.161us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 125.560s 2551.520us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 355.600s 5072.131us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 235.120s 5445.315us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1260.630s 23057.514us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 216.170s 4046.580us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2378.470s 21201.603us 1 1 100.00
chip_sw_aon_timer_irq 235.190s 3624.212us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 238.210s 7055.941us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 438.600s 7699.182us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 369.230s 4608.037us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 341.250s 5355.883us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3189.300s 34866.379us 0 1 0.00
chip_sw_otbn_randomness 600.660s 6350.087us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq 3947.940s 17218.054us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3808.450s 19050.223us 1 1 100.00
chip_sw_otbn_mem_scramble 277.900s 3540.374us 1 1 100.00
chip_sw_rv_core_ibex_rnd 496.810s 4933.253us 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 491.790s 4413.386us 1 1 100.00
chip_sw_aes_enc 219.770s 3278.308us 1 1 100.00
chip_sw_aes_enc_jitter_en 166.740s 3146.288us 1 1 100.00
chip_sw_aes_idle 196.980s 3127.360us 1 1 100.00
chip_sw_aes_masking_off 191.010s 2589.514us 1 1 100.00
chip_sw_alert_test 202.980s 3359.011us 0 1 0.00
chip_sw_alert_handler_escalation 410.360s 6036.682us 1 1 100.00
chip_sw_alert_handler_ping_timeout 285.950s 4519.746us 1 1 100.00
chip_sw_alert_handler_ping_ok 826.720s 7738.036us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8923.500s 256242.144us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 154.320s 3376.903us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.137s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clkoff 1002.950s 8545.119us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 978.990s 8430.751us 1 1 100.00
chip_sw_alert_handler_entropy 189.490s 3722.731us 1 1 100.00
chip_sw_aes_entropy 201.830s 2893.917us 1 1 100.00
chip_sw_entropy_src_kat_test 154.710s 2941.763us 1 1 100.00
chip_sw_edn_auto_mode 483.680s 4036.637us 1 1 100.00
chip_sw_edn_boot_mode 336.490s 2771.646us 1 1 100.00
chip_sw_edn_kat 239.860s 2383.185us 1 1 100.00
chip_sw_edn_sw_mode 989.660s 8508.042us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 486.880s 7840.794us 1 1 100.00
chip_sw_csrng_edn_concurrency 2913.370s 16946.844us 1 1 100.00
chip_sw_csrng_kat_test 154.730s 2957.528us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 235.510s 4466.641us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 138.020s 2953.259us 1 1 100.00
chip_sw_entropy_src_csrng 2129.690s 24674.780us 1 1 100.00
chip_sw_edn_entropy_reqs 840.590s 7604.799us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 817.040s 7952.218us 1 1 100.00
chip_sw_hmac_enc 179.850s 2865.656us 1 1 100.00
chip_sw_hmac_enc_jitter_en 163.230s 2508.083us 1 1 100.00
chip_sw_hmac_enc_idle 147.760s 2744.230us 1 1 100.00
chip_sw_hmac_oneshot 1381.070s 9543.887us 1 1 100.00
chip_sw_hmac_multistream 735.210s 6273.287us 1 1 100.00
chip_sw_keymgr_key_derivation 1479.120s 12261.922us 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1687.610s 11814.104us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1500.900s 12420.951us 1 1 100.00
chip_sw_keymgr_sideload_kmac 856.000s 7618.053us 1 1 100.00
chip_sw_keymgr_sideload_aes 1181.050s 10035.266us 1 1 100.00
chip_sw_keymgr_sideload_otbn 2606.190s 13568.114us 1 1 100.00
chip_sw_kmac_mode_cshake 161.370s 2251.657us 1 1 100.00
chip_sw_kmac_mode_kmac 184.770s 2808.710us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 182.830s 3393.742us 1 1 100.00
chip_sw_kmac_app_rom 183.380s 3426.406us 1 1 100.00
chip_sw_kmac_idle 128.720s 2659.378us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 319.480s 9047.648us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 386.860s 4679.705us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 429.190s 5854.085us 1 1 100.00
chip_sw_sram_ctrl_execution_main 581.420s 8785.675us 1 1 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 477.210s 8937.939us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 590.130s 8692.488us 1 1 100.00
chip_sw_sensor_ctrl_alert 527.740s 6478.368us 1 1 100.00
chip_sw_sensor_ctrl_status 189.880s 3224.467us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 245.970s 5972.195us 1 1 100.00
chip_sw_coremark 9978.450s 71382.325us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1881.320s 20864.194us 1 1 100.00
chip_tl_errors 47.190s 1954.911us 0 1 0.00
chip_prim_tl_access 190.710s 6084.546us 1 1 100.00
chip_plic_all_irqs_0 561.350s 5677.241us 1 1 100.00
chip_plic_all_irqs_10 260.710s 3852.266us 1 1 100.00
chip_plic_all_irqs_20 415.100s 4209.349us 1 1 100.00
chip_sw_plic_sw_irq 176.110s 3176.757us 1 1 100.00
chip_sw_clkmgr_off_peri 648.060s 9132.310us 1 1 100.00
chip_sw_clkmgr_off_aes_trans 391.970s 5044.074us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 235.730s 4390.749us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 243.800s 3910.358us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 232.140s 4989.007us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 304.090s 5853.426us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 367.860s 3804.751us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 412.480s 5255.054us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 377.910s 3802.185us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 387.960s 4322.305us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 417.760s 4144.590us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 417.240s 4877.510us 1 1 100.00
chip_sw_clkmgr_reset_frequency 232.920s 2815.120us 1 1 100.00
chip_sw_clkmgr_jitter_frequency 270.910s 3622.706us 0 1 0.00
chip_sw_clkmgr_jitter 166.460s 2819.177us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 413.960s 4648.097us 1 1 100.00
chip_jtag_csr_rw 1395.090s 17546.005us 1 1 100.00
chip_jtag_mem_access 944.310s 14033.373us 1 1 100.00
chip_sw_ast_clk_outputs 650.600s 8325.115us 1 1 100.00
chip_sw_lc_ctrl_program_error 386.500s 5909.901us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 246.130s 7133.021us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 256.900s 4113.528us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1035.010s 25681.877us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1018.180s 28007.881us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 10.433s 0.000us 0 1 0.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 300.050s 6297.549us 1 1 100.00
chip_rv_dm_ndm_reset_req 351.010s 5368.820us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 246.820s 3458.337us 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 295.050s 5868.519us 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 393.390s 4770.046us 1 1 100.00
chip_tap_straps_dev 196.060s 4169.955us 1 1 100.00
chip_tap_straps_testunlock0 209.730s 4199.201us 1 1 100.00
chip_tap_straps_rma 154.890s 4099.827us 1 1 100.00
chip_tap_straps_prod 484.650s 9005.485us 1 1 100.00
chip_rv_dm_lc_disabled 46.100s 2434.906us 0 1 0.00
chip_sw_rv_core_ibex_address_translation 183.980s 3006.024us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 71.360s 2745.347us 0 1 0.00
chip_sw_rv_core_ibex_icache_invalidate 195.090s 3460.526us 1 1 100.00
chip_sw_usb_ast_clk_calib 198.590s 2921.780us 1 1 100.00
chip_sw_flash_crash_alert 395.350s 6347.659us 1 1 100.00
chip_sw_flash_ctrl_write_clear 232.050s 3426.063us 1 1 100.00
chip_padctrl_attributes 166.050s 4141.812us 1 1 100.00
chip_sw_clkmgr_jitter_reduced_freq 161.700s 3279.590us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 374.260s 4797.547us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 620.350s 7162.636us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4209.380s 25289.697us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 185.860s 3220.023us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 138.230s 2843.562us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1198.640s 11839.740us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 200.660s 3212.169us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 368.580s 5083.238us 1 1 100.00
chip_sw_flash_init_reduced_freq 1240.870s 23332.134us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 4488.100s 31688.177us 1 1 100.00
chip_sw_power_idle_load 231.510s 3837.402us 0 1 0.00
chip_sw_power_sleep_load 191.510s 3493.779us 0 1 0.00
chip_sw_ast_clk_rst_inputs 1016.970s 11120.114us 0 1 0.00
chip_sw_power_virus 1099.960s 6641.739us 1 1 100.00
chip_sw_flash_scrambling_smoketest 167.190s 2629.557us 1 1 100.00
chip_sw_flash_ctrl_mem_protection 575.240s 5374.405us 1 1 100.00
ate_bootstrap_flash_erase 606.950s 10010.260us 0 1 0.00
ate_bootstrap_one_frame 6673.090s 45611.797us 1 1 100.00
ate_bootstrap_disjoint 9882.570s 85162.241us 1 1 100.00
rom_e2e_smoke 3115.050s 15243.726us 1 1 100.00
rom_e2e_shutdown_exception_c 2912.890s 15365.383us 1 1 100.00
rom_e2e_shutdown_output 2648.870s 25628.917us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 56.327s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 27.670s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 20.890s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 29.847s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 22.178s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 121.925s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 45.885s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 24.838s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 40.742s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 12.243s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 210.225s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 85.832s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 70.042s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 152.720s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 68.184s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 19.470s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 18.540s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 19.870s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 20.160s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 19.450s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 21.370s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 22.260s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 25.700s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 20.250s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 19.520s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 19.230s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 21.460s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 25.680s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 19.220s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 18.980s 10.320us 0 1 0.00
rom_e2e_asm_init_test_unlocked0 65.669s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 24.335s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 70.991s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 66.927s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 75.076s 0.000us 0 1 0.00
rom_e2e_jtag_debug_test_unlocked0 188.650s 4343.507us 0 1 0.00
rom_e2e_jtag_debug_dev 507.880s 7463.137us 0 1 0.00
rom_e2e_jtag_debug_rma 437.120s 7632.110us 0 1 0.00
rom_e2e_jtag_inject_test_unlocked0 65.140s 2646.999us 0 1 0.00
rom_e2e_jtag_inject_dev 75.100s 2563.637us 0 1 0.00
rom_e2e_jtag_inject_rma 89.590s 2610.409us 0 1 0.00
rom_e2e_static_critical 3208.380s 16327.778us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_meas 3162.330s 20909.769us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 5970.490s 30076.014us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 5921.320s 28477.604us 1 1 100.00
rom_volatile_raw_unlock 40.628s 0.000us 0 1 0.00
rom_raw_unlock 187.847s 0.000us 0 1 0.00
rom_e2e_self_hash 53.375s 0.000us 0 1 0.00
rom_keymgr_functest 357.080s 4522.621us 0 1 0.00
chip_sw_aes_smoketest 211.570s 3735.029us 1 1 100.00
chip_sw_aon_timer_smoketest 205.030s 3560.237us 1 1 100.00
chip_sw_clkmgr_smoketest 166.770s 3440.667us 1 1 100.00
chip_sw_csrng_smoketest 179.430s 3081.129us 1 1 100.00
chip_sw_entropy_src_smoketest 835.500s 7265.301us 1 1 100.00
chip_sw_gpio_smoketest 234.110s 2942.752us 1 1 100.00
chip_sw_hmac_smoketest 240.830s 3672.836us 1 1 100.00
chip_sw_kmac_smoketest 220.520s 3174.077us 1 1 100.00
chip_sw_otbn_smoketest 972.670s 8090.094us 1 1 100.00
chip_sw_otp_ctrl_smoketest 194.690s 3099.629us 1 1 100.00
chip_sw_pwrmgr_smoketest 198.590s 5211.957us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 314.070s 5897.057us 1 1 100.00
chip_sw_rv_plic_smoketest 134.730s 2315.910us 1 1 100.00
chip_sw_rv_timer_smoketest 190.250s 4022.073us 1 1 100.00
chip_sw_rstmgr_smoketest 210.760s 2929.612us 1 1 100.00
chip_sw_sram_ctrl_smoketest 182.550s 3020.678us 1 1 100.00
chip_sw_uart_smoketest 212.200s 3193.828us 1 1 100.00
xbar_smoke 4.690s 48.521us 1 1 100.00
xbar_smoke_zero_delays 5.880s 47.196us 1 1 100.00
xbar_smoke_large_delays 39.460s 6228.100us 1 1 100.00
xbar_smoke_slow_rsp 41.890s 4398.378us 1 1 100.00
xbar_random 48.510s 2089.064us 1 1 100.00
xbar_random_zero_delays 15.320s 213.732us 1 1 100.00
xbar_random_large_delays 94.690s 15880.512us 1 1 100.00
xbar_random_slow_rsp 149.690s 16851.266us 1 1 100.00
xbar_access_same_device 36.660s 1187.365us 1 1 100.00
xbar_access_same_device_slow_rsp 117.150s 12466.910us 1 1 100.00
xbar_same_source 20.180s 349.409us 1 1 100.00
xbar_error_random 14.410s 234.757us 1 1 100.00
xbar_unmapped_addr 4.100s 39.113us 1 1 100.00
xbar_error_and_unmapped_addr 29.780s 1133.845us 1 1 100.00
xbar_stress_all 187.500s 3230.814us 1 1 100.00
xbar_stress_all_with_rand_reset 603.840s 8864.937us 1 1 100.00
xbar_stress_all_with_error 163.270s 3410.267us 1 1 100.00
xbar_stress_all_with_reset_error 228.270s 5956.776us 1 1 100.00
chip_csr_hw_reset 259.600s 7009.402us 1 1 100.00
chip_csr_rw 247.250s 4691.388us 1 1 100.00
chip_csr_mem_rw_with_rand_reset 356.490s 6176.211us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 31361552707308513943666013200029644290981902418814272725672284269909202845363 None
---- STDERR ----
Another command (pid=2071322) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 63267312920783635020005937921371284678593657658417118862152656323826736331854 None
Another command (pid=411190) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=419105) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=370080) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 78389972501038462934403975615691607637210038679114082377264058130186745620322 None
Another command (pid=588079) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=576623) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=588818) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 13428004467571277130766598915277008574454233013591145216241962763492990918766 None
Another command (pid=396879) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=554894) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=563990) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 30930193501128528724144308875489347565563992514232050390856194590059585496956 None
Another command (pid=597912) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=470710) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=602591) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 107300449915092456022824490536181714709307803370802636052951232044577679545957 None
Another command (pid=582264) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=576623) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=588818) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 98665564256597446563679036378239399373493771624981741430752162994684266231965 None
Another command (pid=451139) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=453437) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=378496) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 37975039637558691800574648766269556677890043650037682279016910700732638534845 None
Another command (pid=451139) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=453437) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=378496) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 33532300649986411871748687445224652396346026543705624410185716143931758128692 None
Another command (pid=453437) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=421806) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=543432) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 87928742764077558978896813636425953546425818125578649265782109179921289078274 None
Another command (pid=396879) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=554894) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=563990) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 107799502692316053433211194113242256432784416685697373117701810611767515875552 None
Another command (pid=560628) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=545254) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=562198) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 113663571192098564820689935317197554429399654110475610673588761806405326711680 None
Another command (pid=709298) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=716090) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=720393) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 22978381074059233208835956477308137272904177159205273375501473845419430804802 None
Another command (pid=563990) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=527143) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=572160) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 94635416857541385582558011421891931149612657133608881488696700978642107426710 None
---- STDERR ----
Another command (pid=551669) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 10532504429438281580704082247588866478963382955212666137057892959150791537107 None
Another command (pid=692065) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=735276) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=600217) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 101663646500824163186286927936519335554741407537673765884381186239330444999610 None
Another command (pid=562198) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=560727) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=554894) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 94494578632895787557200601262979483163883035743493253993078366611773667093037 None
Another command (pid=419105) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=370080) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=387477) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 12176988856156559233747280707560826157657729856678255104273038551174288883235 None
Another command (pid=403410) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=411190) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=419105) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 101454636564418133843003590351126256610287560952620759099120213508020285367640 None
Another command (pid=408498) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=453879) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=455052) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 64196232389533693556482082936421737207777928573480046372989537127112468357497 None
Another command (pid=489210) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=480845) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=469790) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 46920358671894794055682195561958730072897434002962932826361504566661645421888 None
Another command (pid=558711) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=560628) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=545254) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 22252249169567619795523546441497705888965134580295041063303544349712287384711 None
---- STDERR ----
Another command (pid=363896) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=396633) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 96398610906619741000888358096497017859066878640917123785586996318122987144336 None
Another command (pid=686990) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=599969) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=676812) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 100174016927720682492477741095650020176317353286629724482741929250638116809166 None
Another command (pid=419105) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=370080) is running. Waiting for it to complete on the server (server_pid=269160)...
Another command (pid=387477) is running. Waiting for it to complete on the server (server_pid=269160)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 7 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 100606263535381963180844568791442387242224546071559594808839095360096460060235 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 104804869092075785379159618533322260281792188421430895446946780559484246655588 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 2791610199532073317097036320226296500564240595473360218469026657697066543549 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 2795119774793051092647365107762317350613977482457870333779367757137625211789 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 106995529071994353744947343829359446234263336246317100380173301578328816578943 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 68203885061414023114503479383084558839576977075561333450850556734233062523574 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 113442169214178981905643220816059151902816625062288139388666465800364786065915 307
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 100289219284961125356718945691999206069183095055266254709104441448353632232823 366
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 41268379600598006049968574065419670295884797468868315582650078658021019795142 367
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 109987067058024300230191431217626717134732889170616234339427941211085957702201 367
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 94836870789742848615178018409740916537485423447014552333667354799905007748726 328
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 45559610977640634501705610901202366025154642983143741570853213824308837761285 328
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 49754298999871874846301479103086374341469224196321422190429154798864119467384 327
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 69509110008924255832881284325993481673418035813669414159793914777534059519685 325
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 56222940720471020307283288352908592940367936712684717980102737018464777924242 326
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 48700126464539470779478968584379899880714913874042435179518386686679197070456 325
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 2 test runs
chip_sw_lc_walkthrough_prod 37287100516370862009981787830318872447061148112593048034263666983919799235710 369
UVM_INFO @ 7616.632570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 57481954600511146632074560931336685666321518717647860103471676494823344880761 341
UVM_INFO @ 7246.608434 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 2 test runs
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 27157203521567092260058432937018934498522998635287653452790956829695835290878 314
UVM_ERROR @ 5735.440000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5735.440000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 86275574691672831173240997528590080523706933445872089299819244707282885117753 319
UVM_ERROR @ 7699.182500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7699.182500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 2 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 21775687359542574377736769939945638377573583329646160194356600507674088748871 313
UVM_ERROR @ 3101.165133 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3101.165133 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 47346295694707473351919593912846003259932668013921616769997349278978850707362 395
UVM_ERROR @ 19948.343892 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 19948.343892 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 65103547106724976657816053999153499093507080571242557761410820404712935651012 363
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 91864945468378621484023455021684966031498505271062254307929521535573815822640 326
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 15232315866134967215252515168620387372061245411590394501381262361357660591775 367
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 66997412221614773869487011266467997625614782764941389305909321698608269368198 327
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * 1 test run
chip_sw_all_escalation_resets 109424374510589518829577209559502755918322218375492735665038833009090087267048 317
UVM_INFO @ 3216.018180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 64237407536702210398465701204628138448992164633989200602011249247794383865779 301
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 50963939749888462305244836186843219170050341927103553204736560556494246036610 327
UVM_INFO @ 3566.542140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 89676135138368337372196285581706085886779013525575408557609654419571149781495 309
UVM_INFO @ 3279.309427 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 60537505123818452561468446729728806854940350650757608642385851697048977605520 342
UVM_INFO @ 5278.721192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 20703259326302423844822564444284402578896241748245464829849995660871166741147 316
UVM_ERROR @ 3368.201632 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3368.201632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 74252057241154758582815915786682299624216052371123824306606135140618962418638 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_walkthrough_dev 20207011500582837832166266540402728417389635918779872037422212739872516870083 308
UVM_INFO @ 26374.713656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] max attempt reached to get lc status LcTokenError! 1 test run
chip_sw_lc_ctrl_volatile_raw_unlock 22682175253513493032192759385516662196509112932700097618439164148395224230048 308
UVM_INFO @ 26888.532084 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 83694365722974517173069269374102135286940000098984689265911667323113733250175 303
UVM_ERROR @ 1874.793260 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 1874.793260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 27494845778315085071620025371862354141746840975812477537635978752101663200353 332
UVM_INFO @ 34866.379452 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 73108579535849932805705004931140310259192900301249591962082986097153505761370 307
UVM_INFO @ 3359.011045 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 24703225684319895952289915301943415262722683034525883927364839699610453812453 308
UVM_INFO @ 3376.903320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 82257661305835647565372657020907624522306247699454166884342789580967125773642 None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
chip_tl_errors 12199061693023276707695792015855555416017786105648253791961897436821720704270 217
TL item was: req: (cip_tl_seq_item@31688) { a_addr: 'h106dc a_data: 'hee42b25f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h1ba19 d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1954.911200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 12863669956846531135668847260006031628299337402306967049738346456295484563342 343
UVM_INFO @ 3622.706438 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 46914459322301968588618188568513708454711678849633289391909753456435553639104 216
UVM_INFO @ 2434.906491 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. 1 test run
chip_sw_rv_core_ibex_lockstep_glitch 10613884699787521889955752776764504700181285595882705461167191238312588867622 324
UVM_INFO @ 2745.346712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_idle_load 76477781273750717546916002805067359637990029016565576645131138080309098243968 312
UVM_INFO @ 3837.402000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_sleep_load 27875008484474790876069210366398039781079285603652744296926280305104737866068 318
UVM_INFO @ 3493.779000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 34179045039148588618416637004739568294995838909281426662861292821054283794644 327
UVM_INFO @ 11120.113893 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 74819299969885262287714791859513886744435783610579031993779722308923596421157 272
UVM_INFO @ 10010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 22369362054210370818449881785218516373831525123117611139188209255142948447207 325
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 80057712381436253018136469130125440246263466441749991465209503779359171045964 325
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_meas 113568947558872425128757239293774155413587823183304890081180731127729718861677 319
UVM_INFO @ 20909.769429 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 72502620713477053958341910831837716700584413043595740322187757400632054943393 327
UVM_ERROR @ 4522.620970 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4522.620970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---