| unmapped |
|
88.89% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 16 | 18 | 88.89 | |||
| pattgen_smoke | 2.000s | 232.184us | 1 | 1 | 100.00 | |
| pattgen_perf | 465.000s | 87593.859us | 1 | 1 | 100.00 | |
| pattgen_error | 1.000s | 102.655us | 1 | 1 | 100.00 | |
| cnt_rollover | 60.000s | 5160.574us | 1 | 1 | 100.00 | |
| pattgen_inactive_level | 3.000s | 399.504us | 1 | 1 | 100.00 | |
| pattgen_tl_errors | 3.000s | 40.941us | 1 | 1 | 100.00 | |
| pattgen_tl_intg_err | 1.000s | 45.047us | 1 | 1 | 100.00 | |
| pattgen_sec_cm | 2.000s | 266.358us | 1 | 1 | 100.00 | |
| pattgen_stress_all_with_rand_reset | 34.000s | 3748.196us | 0 | 1 | 0.00 | |
| pattgen_stress_all | 2.000s | 82.412us | 0 | 1 | 0.00 | |
| pattgen_intr_test | 1.000s | 20.873us | 1 | 1 | 100.00 | |
| pattgen_alert_test | 1.000s | 37.396us | 1 | 1 | 100.00 | |
| pattgen_csr_hw_reset | 2.000s | 14.282us | 1 | 1 | 100.00 | |
| pattgen_csr_rw | 2.000s | 28.167us | 1 | 1 | 100.00 | |
| pattgen_csr_bit_bash | 3.000s | 140.788us | 1 | 1 | 100.00 | |
| pattgen_csr_aliasing | 1.000s | 65.926us | 1 | 1 | 100.00 | |
| pattgen_same_csr_outstanding | 1.000s | 24.102us | 1 | 1 | 100.00 | |
| pattgen_csr_mem_rw_with_rand_reset | 2.000s | 90.853us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_vseq.sv:1287) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 1 test run | |||
| pattgen_stress_all_with_rand_reset | 22079485735391866108835246874881088362132392815661576915465473210833439976807 | 514 |
UVM_ERROR @ 3722159177 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3722159177 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 9/10
UVM_INFO @ 3722207369 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: | 1 test run | |||
| pattgen_stress_all | 93616783940338235610518944131751360778830375362573414769373116148184664618082 | 130 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11220
|
|