Simulation Results: spi_device/1r1w

 
26/05/2026 15:30:30 DVSim: v1.49.6 sha: cbf0611 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.20 %
  • code
  • 93.19 %
  • assert
  • 95.26 %
  • func
  • 64.14 %
  • line
  • 98.81 %
  • branch
  • 98.09 %
  • cond
  • 96.13 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
unmapped
93.94%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 31 33 93.94
spi_device_csb_read 0.830s 17.871us 1 1 100.00
spi_device_mem_parity 0.710s 3.138us 0 1 0.00
spi_device_ram_cfg 0.840s 7.713us 0 1 0.00
spi_device_tpm_read_hw_reg 8.760s 4361.086us 1 1 100.00
spi_device_tpm_all 12.360s 25044.572us 1 1 100.00
spi_device_tpm_sts_read 0.760s 12.716us 1 1 100.00
spi_device_tpm_rw 1.210s 125.666us 1 1 100.00
spi_device_pass_cmd_filtering 11.670s 6895.673us 1 1 100.00
spi_device_pass_addr_payload_swap 4.810s 3947.605us 1 1 100.00
spi_device_intercept 4.440s 6072.383us 1 1 100.00
spi_device_mailbox 6.210s 1829.590us 1 1 100.00
spi_device_upload 3.400s 259.090us 1 1 100.00
spi_device_cfg_cmd 3.960s 1959.279us 1 1 100.00
spi_device_flash_mode 13.800s 7919.973us 1 1 100.00
spi_device_flash_mode_ignore_cmds 142.560s 31073.344us 1 1 100.00
spi_device_read_buffer_direct 5.130s 1302.314us 1 1 100.00
spi_device_flash_all 156.290s 362411.286us 1 1 100.00
spi_device_flash_and_tpm 59.060s 5017.515us 1 1 100.00
spi_device_flash_and_tpm_min_idle 40.060s 58677.422us 1 1 100.00
spi_device_stress_all 1.010s 35.353us 1 1 100.00
spi_device_sec_cm 1.400s 198.653us 1 1 100.00
spi_device_tl_errors 3.290s 160.460us 1 1 100.00
spi_device_tl_intg_err 11.420s 1274.897us 1 1 100.00
spi_device_intr_test 0.810s 13.552us 1 1 100.00
spi_device_alert_test 0.750s 15.999us 1 1 100.00
spi_device_mem_walk 0.980s 40.116us 1 1 100.00
spi_device_mem_partial_access 1.260s 142.451us 1 1 100.00
spi_device_csr_hw_reset 0.980s 18.581us 1 1 100.00
spi_device_csr_rw 1.640s 240.912us 1 1 100.00
spi_device_csr_bit_bash 19.020s 10415.270us 1 1 100.00
spi_device_csr_aliasing 4.210s 209.068us 1 1 100.00
spi_device_same_csr_outstanding 2.480s 373.938us 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.020s 401.930us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 97030645511183236575227669287139489275209524657828789221626901233057758843593 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 2762829 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 2762829 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[987])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 20173441972693628703121816145366034268479597006070170855850558767499753406638 76
UVM_ERROR @ 4848160 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x259ab0 [1001011001101010110000] vs 0x0 [0])
UVM_ERROR @ 4859160 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8c9f0d [100011001001111100001101] vs 0x0 [0])
UVM_ERROR @ 4957160 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x86b4db [100001101011010011011011] vs 0x0 [0])
UVM_ERROR @ 5041160 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc7913e [110001111001000100111110] vs 0x0 [0])