Simulation Results: uart

 
26/05/2026 15:30:30 DVSim: v1.49.6 sha: cbf0611 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.78 %
  • code
  • 94.98 %
  • assert
  • 98.27 %
  • func
  • 61.08 %
  • line
  • 98.86 %
  • branch
  • 96.50 %
  • cond
  • 93.23 %
  • toggle
  • 91.32 %
Validation stages
unmapped
92.59%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 25 27 92.59
uart_smoke 1.600s 960.482us 1 1 100.00
uart_tx_rx 86.960s 58706.073us 1 1 100.00
uart_fifo_full 27.440s 71363.694us 1 1 100.00
uart_fifo_overflow 74.190s 254274.324us 1 1 100.00
uart_fifo_reset 10.210s 29099.914us 1 1 100.00
uart_rx_oversample 14.450s 2970.103us 1 1 100.00
uart_intr 5.920s 20460.052us 1 1 100.00
uart_noise_filter 15.620s 14544.195us 0 1 0.00
uart_rx_start_bit_filter 2.270s 4717.331us 1 1 100.00
uart_rx_parity_err 44.490s 81830.274us 1 1 100.00
uart_tx_ovrd 1.910s 2101.363us 1 1 100.00
uart_loopback 8.880s 10899.051us 1 1 100.00
uart_perf 704.270s 22017.108us 1 1 100.00
uart_long_xfer_wo_dly 302.260s 103357.483us 1 1 100.00
uart_stress_all_with_rand_reset 36.010s 4921.364us 0 1 0.00
uart_stress_all 80.670s 261892.887us 1 1 100.00
uart_sec_cm 0.840s 65.671us 1 1 100.00
uart_tl_errors 1.560s 393.880us 1 1 100.00
uart_tl_intg_err 1.150s 163.776us 1 1 100.00
uart_intr_test 0.630s 48.392us 1 1 100.00
uart_alert_test 0.710s 11.336us 1 1 100.00
uart_csr_hw_reset 0.670s 12.207us 1 1 100.00
uart_csr_rw 0.740s 119.874us 1 1 100.00
uart_csr_bit_bash 1.390s 257.783us 1 1 100.00
uart_csr_aliasing 0.780s 101.612us 1 1 100.00
uart_same_csr_outstanding 0.760s 62.522us 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.010s 31.206us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 59676225612375073450037241602600831696167359286677226103119649681408547609328 79
UVM_ERROR @ 6652655276 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 6652665276 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (240 [0xf0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 6652675276 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 6652685276 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (240 [0xf0] vs 127 [0x7f]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_stress_all_with_rand_reset 114859589010482294691541212841812191294190815342045551352609425621656609769043 109
UVM_INFO @ 668582560 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/449
UVM_ERROR @ 695322999 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 695333416 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 695406335 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata