Simulation Results: chip

 
27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.84 %
  • code
  • 85.43 %
  • assert
  • 97.37 %
  • func
  • 53.71 %
  • line
  • 94.44 %
  • branch
  • 94.16 %
  • cond
  • 90.17 %
  • toggle
  • 91.25 %
  • FSM
  • 57.14 %
Validation stages
unmapped
76.90%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 253 329 76.90
chip_csr_bit_bash 553.570s 7513.453us 1 1 100.00
chip_csr_aliasing 4929.950s 37578.029us 1 1 100.00
chip_same_csr_outstanding 2892.510s 30604.940us 1 1 100.00
chip_sw_example_flash 130.340s 3260.655us 1 1 100.00
chip_sw_example_rom 74.140s 1846.478us 1 1 100.00
chip_sw_example_manufacturer 215.020s 3553.458us 1 1 100.00
chip_sw_example_concurrency 178.340s 3162.970us 1 1 100.00
chip_sival_flash_info_access 187.100s 3144.515us 1 1 100.00
chip_sw_all_escalation_resets 398.660s 5424.746us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 18.620s 10.340us 0 1 0.00
chip_sw_data_integrity_escalation 424.600s 4922.328us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 159.720s 3353.354us 1 1 100.00
chip_sw_sleep_pin_wake 157.260s 3156.982us 1 1 100.00
chip_sw_sleep_pin_retention 225.770s 4211.837us 1 1 100.00
chip_sw_sleep_pwm_pulses 733.520s 9465.204us 1 1 100.00
chip_sw_pattgen_ios 218.190s 3074.766us 1 1 100.00
chip_sw_uart_tx_rx 399.360s 4577.746us 1 1 100.00
chip_sw_uart_tx_rx_idx1 374.210s 3948.783us 1 1 100.00
chip_sw_uart_tx_rx_idx2 397.680s 4447.439us 1 1 100.00
chip_sw_uart_tx_rx_idx3 420.660s 4684.898us 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7915.150s 63103.427us 1 1 100.00
chip_sw_usbdev_vbus 171.420s 2737.188us 1 1 100.00
chip_sw_usbdev_dpi 1928.020s 12291.959us 1 1 100.00
chip_sw_usbdev_pullup 155.200s 2610.684us 1 1 100.00
chip_sw_usbdev_aon_pullup 288.830s 3777.152us 1 1 100.00
chip_sw_usbdev_setuprx 352.460s 3799.569us 1 1 100.00
chip_sw_usbdev_config_host 1005.620s 8321.802us 1 1 100.00
chip_sw_usbdev_pincfg 5605.280s 32347.859us 1 1 100.00
chip_sw_usbdev_stream 2783.580s 18954.456us 1 1 100.00
chip_sw_usbdev_toggle_restore 178.850s 3099.225us 1 1 100.00
chip_sw_inject_scramble_seed 7529.700s 57995.157us 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7419.620s 55964.074us 1 1 100.00
chip_sw_uart_rand_baudrate 384.760s 3950.542us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1091.690s 9176.693us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 337.490s 4146.805us 1 1 100.00
chip_sw_i2c_host_tx_rx 342.930s 4774.775us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 421.250s 5583.560us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 383.610s 5411.546us 1 1 100.00
chip_sw_i2c_device_tx_rx 308.490s 4034.378us 1 1 100.00
chip_sw_spi_device_tpm 184.470s 3327.282us 1 1 100.00
chip_sw_spi_host_tx_rx 213.420s 2784.114us 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 152.350s 3912.357us 1 1 100.00
chip_sw_spi_device_pass_through 214.890s 3599.237us 1 1 100.00
chip_sw_spi_device_pass_through_collision 158.770s 3519.916us 0 1 0.00
chip_sw_gpio 298.760s 4101.463us 1 1 100.00
chip_sw_flash_ctrl_ops 409.590s 4026.629us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 405.630s 4526.608us 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 161.040s 3520.597us 0 1 0.00
chip_sw_flash_ctrl_access 609.370s 5550.679us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 598.340s 6052.602us 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 240.490s 3381.887us 1 1 100.00
chip_sw_flash_init 1122.050s 18222.018us 1 1 100.00
chip_sw_flash_rma_unlocked 3569.150s 44642.019us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 563.120s 5167.262us 1 1 100.00
chip_sw_kmac_entropy 968.510s 7141.056us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 188.580s 2776.574us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 182.300s 2566.032us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 555.450s 8164.265us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 467.270s 6315.019us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 448.250s 7451.212us 0 1 0.00
chip_sw_otp_ctrl_vendor_test_csr_access 157.540s 2659.410us 1 1 100.00
chip_sw_otp_ctrl_escalation 222.950s 3120.320us 0 1 0.00
chip_sw_otp_ctrl_dai_lock 811.630s 7392.654us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 5.010s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 145.320s 2760.159us 1 1 100.00
chip_sw_otp_ctrl_descrambling 243.020s 3255.284us 1 1 100.00
chip_sw_lc_ctrl_transition 1036.880s 26069.155us 0 1 0.00
chip_sw_lc_ctrl_rma_to_scrap 143.920s 3927.904us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 90.140s 3022.020us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 98.380s 2955.490us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 94.460s 2667.857us 1 1 100.00
chip_sw_lc_walkthrough_dev 615.280s 10492.617us 0 1 0.00
chip_sw_lc_walkthrough_prod 655.830s 8035.372us 0 1 0.00
chip_sw_lc_walkthrough_prodend 524.810s 8582.448us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 75.220s 2248.940us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 65.970s 2656.211us 1 1 100.00
chip_sw_lc_walkthrough_rma 997.990s 25850.085us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 897.090s 26255.504us 0 1 0.00
chip_sw_rstmgr_sw_req 269.970s 5044.634us 1 1 100.00
chip_sw_rstmgr_sw_rst 125.030s 2160.217us 1 1 100.00
chip_sw_rstmgr_alert_info 1113.760s 11351.960us 1 1 100.00
chip_sw_rstmgr_cpu_info 522.310s 7248.941us 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 76.630s 2562.548us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 304.960s 5422.656us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 633.190s 6066.040us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 998.460s 12708.298us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1355.380s 19578.005us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 238.270s 5100.340us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 958.390s 13255.590us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 376.570s 6761.203us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 391.470s 6148.435us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 153.020s 3430.834us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 384.800s 8096.539us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1692.790s 28382.848us 0 1 0.00
chip_sw_pwrmgr_sleep_disabled 220.500s 2738.063us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 302.640s 5026.958us 1 1 100.00
chip_sw_rv_timer_irq 149.200s 2841.722us 1 1 100.00
chip_sw_rv_timer_systick_test 5738.970s 38674.174us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 180.280s 3091.620us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 319.620s 4469.058us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 350.160s 6632.716us 1 1 100.00
chip_sw_sysrst_ctrl_reset 916.990s 21778.215us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 207.540s 3917.598us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2530.750s 19959.171us 1 1 100.00
chip_sw_aon_timer_irq 230.610s 3964.931us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 291.100s 6353.174us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 544.230s 8934.198us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 412.520s 5388.794us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 368.740s 5185.541us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3092.280s 34684.571us 0 1 0.00
chip_sw_otbn_randomness 565.210s 6754.608us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq 3702.570s 16935.106us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3742.920s 19352.796us 1 1 100.00
chip_sw_otbn_mem_scramble 248.560s 3542.415us 1 1 100.00
chip_sw_rv_core_ibex_rnd 522.700s 5000.182us 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 511.680s 5080.985us 1 1 100.00
chip_sw_aes_enc 161.640s 2597.267us 1 1 100.00
chip_sw_aes_enc_jitter_en 180.560s 2865.782us 1 1 100.00
chip_sw_aes_idle 204.330s 3127.768us 1 1 100.00
chip_sw_aes_masking_off 170.030s 3141.667us 1 1 100.00
chip_sw_alert_test 194.690s 3111.221us 0 1 0.00
chip_sw_alert_handler_escalation 374.250s 5050.884us 1 1 100.00
chip_sw_alert_handler_ping_timeout 336.410s 5488.600us 1 1 100.00
chip_sw_alert_handler_ping_ok 748.600s 8782.221us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8018.440s 255465.315us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 136.860s 2817.286us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.160s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clkoff 1060.200s 8358.125us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 731.640s 6082.220us 1 1 100.00
chip_sw_alert_handler_entropy 223.060s 3605.138us 1 1 100.00
chip_sw_aes_entropy 179.690s 3339.983us 1 1 100.00
chip_sw_entropy_src_kat_test 135.600s 2664.720us 1 1 100.00
chip_sw_edn_auto_mode 967.220s 6655.597us 1 1 100.00
chip_sw_edn_boot_mode 310.890s 2960.481us 1 1 100.00
chip_sw_edn_kat 224.100s 2326.181us 1 1 100.00
chip_sw_edn_sw_mode 1445.080s 9993.693us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 565.360s 7121.159us 1 1 100.00
chip_sw_csrng_edn_concurrency 3465.620s 19902.943us 1 1 100.00
chip_sw_csrng_kat_test 162.250s 2725.718us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 184.980s 3422.585us 0 1 0.00
chip_sw_entropy_src_ast_rng_req 179.110s 2976.160us 1 1 100.00
chip_sw_entropy_src_csrng 2172.160s 24153.110us 1 1 100.00
chip_sw_edn_entropy_reqs 818.350s 7640.531us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 805.880s 7609.183us 1 1 100.00
chip_sw_hmac_enc 190.810s 3289.882us 1 1 100.00
chip_sw_hmac_enc_jitter_en 166.940s 3353.873us 1 1 100.00
chip_sw_hmac_enc_idle 231.630s 3358.619us 1 1 100.00
chip_sw_hmac_oneshot 1182.070s 9205.457us 1 1 100.00
chip_sw_hmac_multistream 731.320s 5536.123us 1 1 100.00
chip_sw_keymgr_key_derivation 953.730s 9056.867us 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1800.840s 12424.385us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1431.030s 10679.137us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1357.260s 11427.203us 1 1 100.00
chip_sw_keymgr_sideload_aes 1285.850s 9320.270us 1 1 100.00
chip_sw_keymgr_sideload_otbn 3256.410s 16187.724us 1 1 100.00
chip_sw_kmac_mode_cshake 167.600s 2823.409us 1 1 100.00
chip_sw_kmac_mode_kmac 210.650s 3318.935us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 206.260s 3257.173us 1 1 100.00
chip_sw_kmac_app_rom 136.770s 2693.757us 1 1 100.00
chip_sw_kmac_idle 156.690s 2744.866us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 366.260s 9366.168us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 369.150s 5027.008us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 373.580s 4882.988us 1 1 100.00
chip_sw_sram_ctrl_execution_main 573.170s 8338.229us 1 1 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 597.670s 8975.599us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 566.770s 9415.479us 1 1 100.00
chip_sw_sensor_ctrl_alert 696.950s 6996.305us 1 1 100.00
chip_sw_sensor_ctrl_status 146.940s 3501.338us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 258.310s 5144.351us 1 1 100.00
chip_sw_coremark 9973.340s 71437.473us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2054.490s 25205.708us 1 1 100.00
chip_tl_errors 76.390s 2634.258us 0 1 0.00
chip_prim_tl_access 325.500s 9792.601us 1 1 100.00
chip_plic_all_irqs_0 577.450s 5470.153us 1 1 100.00
chip_plic_all_irqs_10 288.440s 3510.575us 1 1 100.00
chip_plic_all_irqs_20 439.980s 4549.840us 1 1 100.00
chip_sw_plic_sw_irq 167.130s 3173.074us 1 1 100.00
chip_sw_clkmgr_off_peri 877.100s 12009.712us 1 1 100.00
chip_sw_clkmgr_off_aes_trans 308.850s 4378.204us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 320.970s 4556.377us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 260.210s 4222.061us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 281.330s 4688.222us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 272.540s 6505.360us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 383.750s 4244.162us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 386.300s 5008.963us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 375.130s 3959.553us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 392.610s 4925.379us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 381.610s 4386.677us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 429.380s 5363.123us 1 1 100.00
chip_sw_clkmgr_reset_frequency 233.050s 3014.838us 1 1 100.00
chip_sw_clkmgr_jitter_frequency 238.820s 3230.175us 0 1 0.00
chip_sw_clkmgr_jitter 139.390s 2516.692us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 343.490s 4449.610us 1 1 100.00
chip_jtag_csr_rw 1156.230s 14813.036us 1 1 100.00
chip_jtag_mem_access 924.670s 14358.702us 1 1 100.00
chip_sw_ast_clk_outputs 691.660s 8291.959us 1 1 100.00
chip_sw_lc_ctrl_program_error 391.020s 4568.248us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 257.580s 7063.311us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 218.100s 3706.696us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1065.380s 25265.713us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 811.270s 27441.590us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 9.385s 0.000us 0 1 0.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 258.690s 6088.787us 1 1 100.00
chip_rv_dm_ndm_reset_req 359.720s 4625.115us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 206.180s 3039.896us 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 364.780s 7282.939us 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 377.980s 5740.756us 1 1 100.00
chip_tap_straps_dev 177.250s 4552.141us 1 1 100.00
chip_tap_straps_testunlock0 91.030s 2049.955us 1 1 100.00
chip_tap_straps_rma 348.640s 6274.254us 1 1 100.00
chip_tap_straps_prod 78.430s 2493.183us 1 1 100.00
chip_rv_dm_lc_disabled 255.760s 8162.124us 0 1 0.00
chip_sw_rv_core_ibex_address_translation 188.790s 3255.953us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 108.750s 2720.425us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 163.900s 3005.618us 1 1 100.00
chip_sw_usb_ast_clk_calib 226.430s 3709.295us 1 1 100.00
chip_sw_flash_crash_alert 377.940s 5796.150us 1 1 100.00
chip_sw_flash_ctrl_write_clear 238.350s 2894.129us 1 1 100.00
chip_padctrl_attributes 263.410s 5566.561us 1 1 100.00
chip_sw_clkmgr_jitter_reduced_freq 167.210s 2837.233us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 396.280s 4484.518us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 636.640s 7286.584us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3980.010s 25246.565us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 200.100s 3589.416us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 170.390s 3430.544us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 649.440s 7919.471us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 175.570s 2756.688us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 414.850s 5758.127us 1 1 100.00
chip_sw_flash_init_reduced_freq 1096.150s 19256.607us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 2015.080s 15579.578us 1 1 100.00
chip_sw_power_idle_load 189.630s 2858.252us 0 1 0.00
chip_sw_power_sleep_load 197.040s 3027.104us 0 1 0.00
chip_sw_ast_clk_rst_inputs 1605.070s 14833.964us 0 1 0.00
chip_sw_power_virus 1023.140s 6346.967us 1 1 100.00
chip_sw_flash_scrambling_smoketest 136.760s 2614.945us 1 1 100.00
chip_sw_flash_ctrl_mem_protection 560.030s 5197.083us 1 1 100.00
ate_bootstrap_flash_erase 562.870s 10010.380us 0 1 0.00
ate_bootstrap_one_frame 6376.410s 45785.460us 1 1 100.00
ate_bootstrap_disjoint 10261.100s 84004.155us 1 1 100.00
rom_e2e_smoke 3200.200s 15365.057us 1 1 100.00
rom_e2e_shutdown_exception_c 3111.550s 14682.287us 1 1 100.00
rom_e2e_shutdown_output 2611.690s 26399.752us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 50.542s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 12.231s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 16.687s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 16.724s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 14.684s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 142.741s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 79.441s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 61.828s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 34.553s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 30.733s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 63.915s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 192.215s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 73.391s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 64.502s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 76.219s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 19.380s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 23.180s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 20.300s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 20.240s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 23.810s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 21.220s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 20.340s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 20.070s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 28.320s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 22.060s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 19.780s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 20.470s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 20.100s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 20.090s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 20.220s 10.300us 0 1 0.00
rom_e2e_asm_init_test_unlocked0 186.201s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 14.244s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 7.808s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 72.747s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 86.183s 0.000us 0 1 0.00
rom_e2e_jtag_debug_test_unlocked0 205.180s 4707.918us 0 1 0.00
rom_e2e_jtag_debug_dev 208.040s 5126.307us 0 1 0.00
rom_e2e_jtag_debug_rma 449.740s 7370.304us 0 1 0.00
rom_e2e_jtag_inject_test_unlocked0 77.770s 3202.689us 0 1 0.00
rom_e2e_jtag_inject_dev 54.870s 2339.988us 0 1 0.00
rom_e2e_jtag_inject_rma 73.460s 2721.478us 0 1 0.00
rom_e2e_static_critical 3345.370s 15857.808us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_meas 5756.070s 29254.102us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 3190.910s 16765.163us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 5928.470s 28083.675us 1 1 100.00
rom_volatile_raw_unlock 108.177s 0.000us 0 1 0.00
rom_raw_unlock 120.620s 0.000us 0 1 0.00
rom_e2e_self_hash 49.352s 0.000us 0 1 0.00
rom_keymgr_functest 335.030s 4492.266us 0 1 0.00
chip_sw_aes_smoketest 157.180s 3115.014us 1 1 100.00
chip_sw_aon_timer_smoketest 186.430s 3077.937us 1 1 100.00
chip_sw_clkmgr_smoketest 172.960s 2781.202us 1 1 100.00
chip_sw_csrng_smoketest 139.150s 2796.359us 1 1 100.00
chip_sw_entropy_src_smoketest 787.200s 6444.006us 1 1 100.00
chip_sw_gpio_smoketest 204.910s 3366.304us 1 1 100.00
chip_sw_hmac_smoketest 235.880s 3513.490us 1 1 100.00
chip_sw_kmac_smoketest 192.200s 2899.124us 1 1 100.00
chip_sw_otbn_smoketest 1330.390s 9499.385us 1 1 100.00
chip_sw_otp_ctrl_smoketest 194.120s 3681.254us 1 1 100.00
chip_sw_pwrmgr_smoketest 237.150s 5355.131us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 348.730s 6858.324us 1 1 100.00
chip_sw_rv_plic_smoketest 130.750s 2873.609us 1 1 100.00
chip_sw_rv_timer_smoketest 154.130s 2587.887us 1 1 100.00
chip_sw_rstmgr_smoketest 118.880s 2959.497us 1 1 100.00
chip_sw_sram_ctrl_smoketest 140.360s 2436.699us 1 1 100.00
chip_sw_uart_smoketest 146.030s 2956.454us 1 1 100.00
xbar_smoke 7.220s 230.873us 1 1 100.00
xbar_smoke_zero_delays 4.580s 45.108us 1 1 100.00
xbar_smoke_large_delays 56.420s 8704.410us 1 1 100.00
xbar_smoke_slow_rsp 60.400s 5810.534us 1 1 100.00
xbar_random 34.800s 1386.243us 1 1 100.00
xbar_random_zero_delays 28.670s 468.274us 1 1 100.00
xbar_random_large_delays 104.880s 16209.519us 1 1 100.00
xbar_random_slow_rsp 159.920s 16283.053us 1 1 100.00
xbar_access_same_device 32.630s 580.175us 1 1 100.00
xbar_access_same_device_slow_rsp 393.320s 43053.069us 1 1 100.00
xbar_same_source 12.040s 333.649us 1 1 100.00
xbar_error_random 26.560s 1194.028us 1 1 100.00
xbar_unmapped_addr 7.300s 64.097us 1 1 100.00
xbar_error_and_unmapped_addr 14.760s 493.667us 1 1 100.00
xbar_stress_all 244.780s 10958.226us 1 1 100.00
xbar_stress_all_with_rand_reset 601.580s 10519.903us 1 1 100.00
xbar_stress_all_with_error 137.910s 5352.556us 1 1 100.00
xbar_stress_all_with_reset_error 376.600s 11159.308us 1 1 100.00
chip_csr_hw_reset 281.700s 6418.351us 1 1 100.00
chip_csr_rw 507.380s 5947.151us 1 1 100.00
chip_csr_mem_rw_with_rand_reset 338.820s 6634.095us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 49208869985676527833970160468357396683403132494573198000035213144457254230664 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 23760623113511833128479042543232836088998631553564153543506639957345378104234 None
---- STDERR ----
Another command (pid=359503) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 29241370267644630680798096274039395571521982124940058366330279391188835707874 None
Another command (pid=556407) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=548958) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=460256) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 61727666146105715775819157314512590409903402228185338960948314967680028783409 None
Another command (pid=398275) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=547655) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=564026) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 95468771510573705003010235895702470054926582292752912399096593772505805125923 None
Another command (pid=547655) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=558743) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=570615) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 72128165217945573192271939297600657552669241352384430883645901594965579116502 None
Another command (pid=440250) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=558463) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=398275) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 80008033608389614940686290931459072529030565297636669127610011074147543394524 None
Another command (pid=398275) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=565856) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=547655) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 16084291583421389221095101086177477273133549906272268979231485822002328990253 None
Another command (pid=565856) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=547655) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=564026) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 107878048725692691063501058631627580925546894591489561891267774040569154341085 None
Another command (pid=459560) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=531508) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=534235) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 66296520081860290016285468429652212751793773196333087933441645853968136654259 None
Another command (pid=459560) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=531508) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=534235) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 25756560929899800663734265350878304871459249584155903818650311375500253911471 None
Another command (pid=396994) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=586629) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=579102) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 51619860751347658465555496117893016547813643318470061232376027443902020698935 None
---- STDERR ----
Another command (pid=440848) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 52029589844331515833057161218830988660858814967009579081960018226141851933935 None
Another command (pid=736166) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=802006) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=803170) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 86199991696145764778073919566812001515299424335579929158729339415505714751384 None
Another command (pid=459560) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=531508) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=534235) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 35472078772315011506414503204739494190630017578682520896994706274623460296611 None
---- STDERR ----
Another command (pid=531508) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 35824786340470355395688180364307031318347615152378702495146841306311130028074 None
---- STDERR ----
Another command (pid=557424) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 73616884612215147259187749096968190971113107406208269842607747262180593930563 None
Another command (pid=624498) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=620225) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=639104) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 82650904715256293998410105908340297459579498137159239617378643966309225400226 None
Another command (pid=359503) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=395365) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=400436) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 105055110472704102779730420955484962715627962483785379600943174326418193990086 None
---- STDERR ----
Another command (pid=359503) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=395365) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 113106669176510576453727693456234989470659069496923123860431621066376742187648 None
Another command (pid=440848) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=430944) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=440495) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 58256074538996144195643933886455672677802390484163125483764414491797173269246 None
Another command (pid=539566) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=548958) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=460256) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 2782573573495104867584125163285189856711717759066395913739467293326144812515 None
Another command (pid=459560) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=531508) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=534235) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 78870179776408866281333948648954074348859564949881011449819790556538093344029 None
Another command (pid=556407) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=548958) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=460256) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 57063533147684511182443421813699075921103246979490859472633951769677037274610 None
---- STDERR ----
Another command (pid=359503) is running. Waiting for it to complete on the server (server_pid=250689)...
Another command (pid=376488) is running. Waiting for it to complete on the server (server_pid=250689)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 6 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 53297517392620388804650849559494788922590016217874906673590560721869149168886 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 51997120536771331626224559318227767567104944231129221445490644059603337785163 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 26464986429391749238209705586870784506862934836203863125654970080166325449938 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 68890072984483665749603427715707481286382765285530524439776587482294044920502 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 12377836901867052483891672850844774780864906004841895861381362102884212105517 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 71500941020396865721580499862014475495474369137117215502188176583834604937857 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 54158933341753595921082134729646296751526210520394929870452785447518593342001 368
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 29712080599371921043782780742716104122969563535626347071607016265830575697475 363
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 1816468782350555750544895958669362219529863612531808717612094163807828487210 366
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 96227392839946729686092156961941830503841541897697217911116174837093759727070 327
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 1817536162131720226903208338790138850458012705978717853725401442007576400088 328
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 4509947937799871089069806223352553376221078216837015932004426492772355621835 328
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 3 test runs
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 20396889525542224305895353130349050129775158758069796876418714555690932590919 314
UVM_ERROR @ 5100.340000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5100.340000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 66877064356870283983330570895660512497296353366875982863671139226374470266292 422
UVM_ERROR @ 28382.848000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 28382.848000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 49683826686679814461145460960539232982627998310768490191292627421018239650598 319
UVM_ERROR @ 8934.197500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8934.197500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 112030701192024906692740588139389401231559385148294902706322146234752692865108 328
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 30134268645528493754728856463934276802245332244198238300319484248548006671008 326
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 42292613068011902828021289951777954724984575889590462594136418215083657574864 328
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 2 test runs
chip_sw_otp_ctrl_escalation 17168126594476990544456849554845398563228633070763022555312083031786805976475 316
UVM_ERROR @ 3120.319744 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3120.319744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 84360249279176278033662893928829986110740109415222784206316088300186177991235 312
UVM_ERROR @ 3422.585152 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3422.585152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 2 test runs
chip_sw_lc_walkthrough_dev 17375444366650092909267551800293103259021970230174111014162514667905163031939 369
UVM_INFO @ 10492.616942 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 29341513425914020248312538560600645981334440074382944969301562687375474255374 369
UVM_INFO @ 8035.372312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 34137150510333022143380441931384485085887231388737785779606667381841009133255 362
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 55077321032220340370318203415440596146112852813524885045565858349457692010503 325
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 50698009547415083652444048106364970171034110048694376847883807587033947511 368
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 69926425926181603444561643099935299006362166431579384969883002917860482298662 327
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 49430803854518352854755804057006941202641957444547139761228689728392988672501 301
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 84275257007420146495194441372878795475442873421963226345907871350500770176552 327
UVM_INFO @ 3519.915928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 96426029110277240830646877151820318917089817645446760247033551940489646679634 309
UVM_INFO @ 3520.596555 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 25684830125735459439981894086009691930419832056585255895070881730237496270388 342
UVM_INFO @ 7451.212275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 89298493707957890993738284726240831621166088267020366791306763627819623291993 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_ctrl_transition 36327221263529523793625277727683949671727689268553965166608824031966614199039 305
UVM_INFO @ 26069.155125 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_walkthrough_rma 35564145407988438477916784505894478996307700996227309440867031089401785841663 308
UVM_INFO @ 25850.084688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_walkthrough_testunlocks 56589576787256345985343782754032383029992936893653911468188766142026114644082 304
UVM_INFO @ 26255.503943 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 27990777085952242531357891817362357069632842028604652468499195877959447478834 303
UVM_ERROR @ 2562.547867 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2562.547867 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 30944636209641615199261100555029963833301703765444361782322553455057223805439 313
UVM_ERROR @ 3430.834120 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3430.834120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 103734974769064025671804929602124770889629312623576754210203883809046218197719 332
UVM_INFO @ 34684.570795 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 110074038028380378133011219934973441694567361472390385407353368355505697130261 307
UVM_INFO @ 3111.220990 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 55120854327509172844041434963711412176321322559948643328663302904397096560906 308
UVM_INFO @ 2817.286048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 78612978877893437121959814196162526381936779889347595224966372267654770248496 None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
chip_tl_errors 18657231918890341827319230578706717083507526942635271550762448884720374380156 217
TL item was: req: (cip_tl_seq_item@38500) { a_addr: 'h104b8 a_data: 'h3dbf7c1b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3b a_opcode: 'h4 a_user: 'h18de5 d_param: 'h0 d_source: 'h3b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2634.257605 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 63777127027630993992024929881205517119844477252445971649621196477899143383645 343
UVM_INFO @ 3230.174986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 94132229690037280965950875502429770694857401622996663420429320081762930897358 247
UVM_INFO @ 8162.124113 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_idle_load 60538332585232476464726249101277729953649795321626578390751100808217155831466 312
UVM_INFO @ 2858.252000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_sleep_load 87198377342455073669730637454152917597721837142806631430493572634828816001685 318
UVM_INFO @ 3027.104000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 85892544839398166634026622855968785768401366988303491755974779433108760963158 327
UVM_INFO @ 14833.964045 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 55407829166868092886306333497841023091163570278716450481642113797785399240004 272
UVM_INFO @ 10010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 89532467715232045820950475676486990529071872804046811555898247828878483016954 325
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 25542070821625419941126943317559773910670653092510152945287346894126175058961 328
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds 1 test run
rom_e2e_jtag_debug_dev 105016416337078433467508482627560819139021084447785927147440483025426957694315 318
UVM_INFO @ 5126.306625 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_no_meas 108951352243099055245366129116542471334336447238850237042865953487516064778786 319
UVM_INFO @ 16765.162673 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 104687395226073708171891045190316102908100500139716504434731490327344310641487 327
UVM_ERROR @ 4492.266208 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4492.266208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---