Simulation Results: clkmgr

 
27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.31 %
  • code
  • 96.94 %
  • assert
  • 92.94 %
  • func
  • 84.05 %
  • line
  • 98.54 %
  • branch
  • 97.85 %
  • cond
  • 89.59 %
  • toggle
  • 98.71 %
  • FSM
  • 100.00 %
Validation stages
unmapped
85.19%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 23 27 85.19
clkmgr_smoke 0.850s 45.107us 1 1 100.00
clkmgr_extclk 0.880s 112.453us 1 1 100.00
clkmgr_frequency 3.160s 557.884us 1 1 100.00
clkmgr_frequency_timeout 5.520s 2490.797us 1 1 100.00
clkmgr_peri 0.800s 45.741us 1 1 100.00
clkmgr_trans 0.780s 36.055us 1 1 100.00
clkmgr_clk_status 0.790s 82.634us 1 1 100.00
clkmgr_idle_intersig_mubi 0.930s 47.980us 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.850s 42.425us 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.750s 48.022us 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.830s 45.750us 1 1 100.00
clkmgr_div_intersig_mubi 0.900s 45.553us 1 1 100.00
clkmgr_regwen 2.040s 553.829us 1 1 100.00
clkmgr_shadow_reg_errors 366.330s 200000.000us 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 497.260s 200000.000us 0 1 0.00
clkmgr_sec_cm 0.880s 34.851us 0 1 0.00
clkmgr_stress_all_with_rand_reset 65.560s 19938.834us 1 1 100.00
clkmgr_stress_all 34.100s 7803.161us 1 1 100.00
clkmgr_tl_errors 1.690s 141.133us 1 1 100.00
clkmgr_tl_intg_err 31.760s 10115.560us 0 1 0.00
clkmgr_alert_test 0.740s 42.125us 1 1 100.00
clkmgr_csr_hw_reset 0.860s 68.141us 1 1 100.00
clkmgr_csr_rw 0.790s 18.476us 1 1 100.00
clkmgr_csr_bit_bash 3.310s 325.864us 1 1 100.00
clkmgr_csr_aliasing 1.160s 45.951us 1 1 100.00
clkmgr_same_csr_outstanding 0.900s 36.632us 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.900s 22.970us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
clkmgr_shadow_reg_errors 55170826379174035114862866333072034180693902846843259204022338225835533004067 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 96794612791471540666515068806342471451495929484334156437347735979385364011276 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 37550161110449114406468221045878246312018567680414053080807880451815096215992 99
UVM_INFO @ 34851142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_tl_intg_err 53963390813728903388011684656946912524949023695905722339244765062400599726745 151
UVM_INFO @ 10115559967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---