Simulation Results: i2c

 
27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.74 %
  • code
  • 81.73 %
  • assert
  • 97.25 %
  • func
  • 84.25 %
  • line
  • 96.54 %
  • branch
  • 92.55 %
  • cond
  • 87.03 %
  • toggle
  • 89.66 %
  • FSM
  • 42.86 %
Validation stages
unmapped
84.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 42 50 84.00
i2c_host_smoke 20.490s 1791.128us 1 1 100.00
i2c_host_override 0.930s 73.007us 1 1 100.00
i2c_host_fifo_watermark 80.070s 5624.532us 1 1 100.00
i2c_host_fifo_overflow 35.890s 4069.012us 1 1 100.00
i2c_host_fifo_reset_fmt 1.240s 700.719us 1 1 100.00
i2c_host_fifo_fmt_empty 6.930s 1163.159us 1 1 100.00
i2c_host_fifo_reset_rx 3.090s 620.250us 1 1 100.00
i2c_host_fifo_full 134.860s 5057.187us 1 1 100.00
i2c_host_perf 6.510s 6940.148us 1 1 100.00
i2c_host_perf_precise 69.440s 2355.570us 1 1 100.00
i2c_host_stretch_timeout 6.420s 3489.437us 1 1 100.00
i2c_host_error_intr 3.000s 117.478us 0 1 0.00
i2c_host_stress_all 569.960s 154823.924us 1 1 100.00
i2c_target_glitch 2.370s 915.443us 0 1 0.00
i2c_target_smoke 7.690s 5487.748us 1 1 100.00
i2c_target_stress_wr 22.350s 29222.123us 1 1 100.00
i2c_target_stress_rd 21.210s 6209.608us 1 1 100.00
i2c_target_stretch 11.850s 2227.243us 1 1 100.00
i2c_target_intr_smoke 2.570s 590.575us 1 1 100.00
i2c_target_intr_stress_wr 33.550s 11094.120us 1 1 100.00
i2c_target_timeout 5.190s 5794.380us 1 1 100.00
i2c_target_unexp_stop 0.890s 159.176us 0 1 0.00
i2c_target_fifo_reset_acq 1.200s 569.945us 1 1 100.00
i2c_target_fifo_reset_tx 0.750s 179.836us 1 1 100.00
i2c_target_perf 2.490s 2087.012us 1 1 100.00
i2c_target_stress_all 199.100s 41085.300us 1 1 100.00
i2c_target_bad_addr 3.340s 4284.033us 1 1 100.00
i2c_target_hrst 6.710s 10777.765us 0 1 0.00
i2c_host_stress_all_with_rand_reset 7.850s 1150.922us 0 1 0.00
i2c_target_stress_all_with_rand_reset 9.960s 3428.002us 0 1 0.00
i2c_host_mode_toggle 1.320s 281.692us 0 1 0.00
i2c_host_may_nack 7.400s 265.228us 1 1 100.00
i2c_target_fifo_watermarks_acq 2.170s 2350.794us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.410s 159.185us 1 1 100.00
i2c_target_tx_stretch_ctrl 6.770s 689.261us 1 1 100.00
i2c_target_smbus_maxlen 1.900s 999.641us 1 1 100.00
i2c_target_nack_acqfull 2.800s 557.261us 1 1 100.00
i2c_target_nack_acqfull_addr 2.570s 506.607us 1 1 100.00
i2c_target_nack_txstretch 1.310s 640.260us 0 1 0.00
i2c_tl_errors 2.790s 2927.314us 1 1 100.00
i2c_tl_intg_err 1.510s 345.550us 1 1 100.00
i2c_sec_cm 1.080s 241.207us 1 1 100.00
i2c_intr_test 0.870s 59.746us 1 1 100.00
i2c_alert_test 0.810s 17.067us 1 1 100.00
i2c_csr_hw_reset 0.880s 17.098us 1 1 100.00
i2c_csr_rw 0.840s 18.738us 1 1 100.00
i2c_csr_bit_bash 2.340s 1614.256us 1 1 100.00
i2c_csr_aliasing 1.770s 209.191us 1 1 100.00
i2c_same_csr_outstanding 1.160s 26.461us 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.000s 209.255us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 2 test runs
i2c_host_error_intr 48348603278769913348522118444091034644504929014455192366096859482653395240241 104
UVM_INFO @ 117477639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 28594443520957687278546962378573383276399191328617108347855076554110738341825 154
UVM_INFO @ 3428002262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 29890749490850495210125988285331708122093857185831969049291444255127230004389 84
UVM_INFO @ 915442747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 46321070552119615106315886279637142740382352675028274423698329586521601129381 78
UVM_INFO @ 159175645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! 1 test run
i2c_target_hrst 11367314793589102286343456629288576336893438961929823511914139413925093940295 79
UVM_INFO @ 10777765282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 98740790214278997471488909638962627627488489837771111064919688725799416591418 86
UVM_INFO @ 1150922070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: 1 test run
i2c_host_mode_toggle 84929936849277074515766079077749555619952720091430446669193944217288596916645 85
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @10327
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * 1 test run
i2c_target_nack_txstretch 45273414435126708424194393097096423892118307857531321695690033842077447892117 78
UVM_INFO @ 640259928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---