| unmapped |
|
83.33% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 15 | 18 | 83.33 | |||
| pattgen_smoke | 2.000s | 21.473us | 1 | 1 | 100.00 | |
| pattgen_perf | 2992.000s | 600000.000us | 0 | 1 | 0.00 | |
| pattgen_error | 2.000s | 110.142us | 1 | 1 | 100.00 | |
| cnt_rollover | 31.000s | 2736.444us | 1 | 1 | 100.00 | |
| pattgen_inactive_level | 2.000s | 127.990us | 1 | 1 | 100.00 | |
| pattgen_tl_errors | 2.000s | 25.652us | 1 | 1 | 100.00 | |
| pattgen_tl_intg_err | 1.000s | 177.604us | 1 | 1 | 100.00 | |
| pattgen_sec_cm | 1.000s | 155.110us | 1 | 1 | 100.00 | |
| pattgen_stress_all_with_rand_reset | 23.000s | 2880.762us | 0 | 1 | 0.00 | |
| pattgen_stress_all | 7303.000s | 1346250.648us | 0 | 1 | 0.00 | |
| pattgen_intr_test | 1.000s | 29.783us | 1 | 1 | 100.00 | |
| pattgen_alert_test | 2.000s | 98.905us | 1 | 1 | 100.00 | |
| pattgen_csr_hw_reset | 1.000s | 16.758us | 1 | 1 | 100.00 | |
| pattgen_csr_rw | 1.000s | 39.227us | 1 | 1 | 100.00 | |
| pattgen_csr_bit_bash | 2.000s | 73.412us | 1 | 1 | 100.00 | |
| pattgen_csr_aliasing | 2.000s | 56.401us | 1 | 1 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 102.955us | 1 | 1 | 100.00 | |
| pattgen_csr_mem_rw_with_rand_reset | 2.000s | 45.464us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 1 test run | |||
| pattgen_perf | 114967999759949862738802666770847756921390794628140544944916013371625043874646 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1287) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 1 test run | |||
| pattgen_stress_all_with_rand_reset | 94409761384633529467500974522864621447973293046258181740372562317627462571538 | 121 |
UVM_ERROR @ 703067462 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 703067462 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 703230726 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: | 1 test run | |||
| pattgen_stress_all | 114525851550890247906723352047516773532128647629971928274177970941370997549656 | 158 |
----------------------------------------
Name Type Size Value
----------------------------------------
exp_item pattgen_item - @11339
|
|