Simulation Results: rv_timer

 
27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.17 %
  • code
  • 99.46 %
  • assert
  • 97.45 %
  • func
  • 70.59 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 97.85 %
  • toggle
  • 100.00 %
Validation stages
unmapped
84.21%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 16 19 84.21
rv_timer_random 0.580s 15.206us 1 1 100.00
rv_timer_min 0.570s 25.834us 1 1 100.00
rv_timer_max 0.590s 89.063us 0 1 0.00
rv_timer_disabled 2.160s 1621.755us 1 1 100.00
rv_timer_cfg_update_on_fly 122.810s 108269.427us 1 1 100.00
rv_timer_random_reset 1.940s 97.842us 0 1 0.00
rv_timer_stress_all_with_rand_reset 4.840s 894.247us 0 1 0.00
rv_timer_stress_all 0.690s 51.905us 1 1 100.00
rv_timer_sec_cm 0.810s 186.841us 1 1 100.00
rv_timer_tl_errors 0.810s 79.405us 1 1 100.00
rv_timer_tl_intg_err 1.120s 488.611us 1 1 100.00
rv_timer_intr_test 0.600s 12.236us 1 1 100.00
rv_timer_alert_test 0.560s 17.634us 1 1 100.00
rv_timer_csr_hw_reset 0.590s 17.269us 1 1 100.00
rv_timer_csr_rw 0.570s 14.492us 1 1 100.00
rv_timer_csr_bit_bash 2.890s 5216.061us 1 1 100.00
rv_timer_csr_aliasing 0.730s 81.785us 1 1 100.00
rv_timer_same_csr_outstanding 0.740s 54.555us 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.870s 25.472us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 115737004973153918946244986837275677198624002520708025160337660989057021304279 75
UVM_INFO @ 89063441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_random_reset 65792660694368545865852754807868825284851174220143382530924174590995439659330 75
UVM_INFO @ 97841747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 1 test run
rv_timer_stress_all_with_rand_reset 43077713235947153221018003622995174374077640888992612836311084252254043991400 119
UVM_INFO @ 894246962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---