Simulation Results: spi_device/1r1w

 
27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.65 %
  • code
  • 93.09 %
  • assert
  • 95.51 %
  • func
  • 68.35 %
  • line
  • 98.86 %
  • branch
  • 98.20 %
  • cond
  • 95.51 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
unmapped
93.94%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 31 33 93.94
spi_device_csb_read 0.760s 44.424us 1 1 100.00
spi_device_mem_parity 0.720s 2.647us 0 1 0.00
spi_device_ram_cfg 0.800s 4.219us 0 1 0.00
spi_device_tpm_read_hw_reg 8.100s 6265.595us 1 1 100.00
spi_device_tpm_all 37.160s 21823.553us 1 1 100.00
spi_device_tpm_sts_read 0.830s 47.719us 1 1 100.00
spi_device_tpm_rw 1.760s 217.042us 1 1 100.00
spi_device_pass_cmd_filtering 7.660s 17807.898us 1 1 100.00
spi_device_pass_addr_payload_swap 24.080s 11716.589us 1 1 100.00
spi_device_intercept 2.760s 122.142us 1 1 100.00
spi_device_mailbox 8.090s 1676.379us 1 1 100.00
spi_device_upload 4.030s 692.095us 1 1 100.00
spi_device_cfg_cmd 2.130s 715.568us 1 1 100.00
spi_device_flash_mode 8.130s 13179.305us 1 1 100.00
spi_device_flash_mode_ignore_cmds 58.100s 28221.788us 1 1 100.00
spi_device_read_buffer_direct 9.750s 11152.631us 1 1 100.00
spi_device_flash_all 97.270s 60408.177us 1 1 100.00
spi_device_flash_and_tpm 46.170s 14076.877us 1 1 100.00
spi_device_flash_and_tpm_min_idle 257.170s 275968.209us 1 1 100.00
spi_device_stress_all 0.900s 156.569us 1 1 100.00
spi_device_sec_cm 1.350s 94.654us 1 1 100.00
spi_device_tl_errors 1.670s 73.696us 1 1 100.00
spi_device_tl_intg_err 4.460s 112.918us 1 1 100.00
spi_device_intr_test 0.750s 15.002us 1 1 100.00
spi_device_alert_test 0.660s 16.679us 1 1 100.00
spi_device_mem_walk 0.670s 13.675us 1 1 100.00
spi_device_mem_partial_access 1.540s 24.774us 1 1 100.00
spi_device_csr_hw_reset 0.960s 18.824us 1 1 100.00
spi_device_csr_rw 1.810s 38.794us 1 1 100.00
spi_device_csr_bit_bash 27.740s 4130.786us 1 1 100.00
spi_device_csr_aliasing 16.700s 7715.297us 1 1 100.00
spi_device_same_csr_outstanding 1.550s 65.917us 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.960s 78.234us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 10438136497618769214465351494586179634177091077422240661753401142166693469635 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 2230550 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 2230550 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[914])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 62876567580700449422481643054327375477851507002375945934709193691242881558072 76
UVM_ERROR @ 1933398 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x41a34a [10000011010001101001010] vs 0x0 [0])
UVM_ERROR @ 1996398 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x47096 [1000111000010010110] vs 0x0 [0])
UVM_ERROR @ 2011398 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x57a1d0 [10101111010000111010000] vs 0x0 [0])
UVM_ERROR @ 2072398 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xaf303a [101011110011000000111010] vs 0x0 [0])