Simulation Results: uart

 
27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.22 %
  • code
  • 95.87 %
  • assert
  • 98.85 %
  • func
  • 51.95 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.33 %
  • toggle
  • 91.55 %
Validation stages
unmapped
96.30%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 26 27 96.30
uart_smoke 1.370s 494.539us 1 1 100.00
uart_tx_rx 26.340s 66317.805us 1 1 100.00
uart_fifo_full 14.500s 51859.852us 1 1 100.00
uart_fifo_overflow 105.530s 86520.343us 1 1 100.00
uart_fifo_reset 14.980s 10328.912us 1 1 100.00
uart_rx_oversample 11.410s 7118.750us 1 1 100.00
uart_intr 73.330s 80038.190us 1 1 100.00
uart_noise_filter 2.990s 1010.549us 0 1 0.00
uart_rx_start_bit_filter 3.050s 1812.316us 1 1 100.00
uart_rx_parity_err 62.910s 95806.424us 1 1 100.00
uart_tx_ovrd 15.630s 6112.907us 1 1 100.00
uart_loopback 4.560s 5565.725us 1 1 100.00
uart_perf 76.850s 10208.144us 1 1 100.00
uart_long_xfer_wo_dly 540.410s 127688.731us 1 1 100.00
uart_stress_all_with_rand_reset 6.690s 894.077us 1 1 100.00
uart_stress_all 54.940s 93342.345us 1 1 100.00
uart_sec_cm 0.880s 116.410us 1 1 100.00
uart_tl_errors 2.680s 260.197us 1 1 100.00
uart_tl_intg_err 1.150s 76.931us 1 1 100.00
uart_intr_test 0.690s 14.772us 1 1 100.00
uart_alert_test 0.830s 17.268us 1 1 100.00
uart_csr_hw_reset 0.920s 16.060us 1 1 100.00
uart_csr_rw 0.640s 15.231us 1 1 100.00
uart_csr_bit_bash 1.590s 160.760us 1 1 100.00
uart_csr_aliasing 1.010s 37.516us 1 1 100.00
uart_same_csr_outstanding 0.750s 22.752us 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.980s 125.149us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 96912248476585795092337552240457066541584895231217678879241415882323503557784 74
UVM_ERROR @ 15359418 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 24204540 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 24204540 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 245394444 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0