Simulation Results: chip

 
28/05/2026 15:30:27 DVSim: v1.49.6 sha: 1d0cf80 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.73 %
  • code
  • 84.70 %
  • assert
  • 97.37 %
  • func
  • 36.12 %
  • line
  • 93.98 %
  • branch
  • 92.30 %
  • cond
  • 88.84 %
  • toggle
  • 91.25 %
  • FSM
  • 57.14 %
Validation stages
unmapped
75.99%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 250 329 75.99
chip_csr_bit_bash 172.170s 3294.651us 1 1 100.00
chip_csr_aliasing 4603.080s 37015.627us 1 1 100.00
chip_same_csr_outstanding 2729.670s 27364.237us 1 1 100.00
chip_sw_example_flash 157.960s 2339.615us 1 1 100.00
chip_sw_example_rom 84.460s 2669.194us 1 1 100.00
chip_sw_example_manufacturer 169.260s 3020.927us 1 1 100.00
chip_sw_example_concurrency 178.250s 3421.591us 1 1 100.00
chip_sival_flash_info_access 205.570s 3746.554us 1 1 100.00
chip_sw_all_escalation_resets 355.550s 5830.146us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 19.210s 10.160us 0 1 0.00
chip_sw_data_integrity_escalation 558.780s 5643.038us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 172.470s 3367.021us 0 1 0.00
chip_sw_sleep_pin_wake 163.080s 3046.433us 1 1 100.00
chip_sw_sleep_pin_retention 219.730s 4027.286us 1 1 100.00
chip_sw_sleep_pwm_pulses 827.980s 9471.796us 1 1 100.00
chip_sw_pattgen_ios 183.800s 3056.160us 1 1 100.00
chip_sw_uart_tx_rx 344.310s 3659.558us 1 1 100.00
chip_sw_uart_tx_rx_idx1 340.780s 4684.746us 1 1 100.00
chip_sw_uart_tx_rx_idx2 350.340s 4184.934us 1 1 100.00
chip_sw_uart_tx_rx_idx3 381.990s 4507.825us 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8011.340s 63470.902us 1 1 100.00
chip_sw_usbdev_vbus 126.640s 2463.964us 1 1 100.00
chip_sw_usbdev_dpi 1879.820s 11927.731us 1 1 100.00
chip_sw_usbdev_pullup 155.900s 3187.100us 1 1 100.00
chip_sw_usbdev_aon_pullup 313.800s 4126.277us 1 1 100.00
chip_sw_usbdev_setuprx 340.550s 4628.945us 1 1 100.00
chip_sw_usbdev_config_host 1038.810s 8659.330us 1 1 100.00
chip_sw_usbdev_pincfg 5399.120s 31913.796us 1 1 100.00
chip_sw_usbdev_stream 3189.720s 18974.580us 1 1 100.00
chip_sw_usbdev_toggle_restore 178.220s 2856.409us 1 1 100.00
chip_sw_inject_scramble_seed 7593.120s 57794.570us 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7420.050s 54256.754us 1 1 100.00
chip_sw_uart_rand_baudrate 299.720s 3706.359us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 332.540s 4207.960us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 673.820s 8837.693us 1 1 100.00
chip_sw_i2c_host_tx_rx 361.830s 4952.737us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 418.380s 5375.780us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 463.060s 5520.156us 1 1 100.00
chip_sw_i2c_device_tx_rx 329.900s 4557.994us 1 1 100.00
chip_sw_spi_device_tpm 205.140s 2871.417us 1 1 100.00
chip_sw_spi_host_tx_rx 190.240s 3451.580us 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 151.870s 4029.195us 1 1 100.00
chip_sw_spi_device_pass_through 247.310s 4121.956us 1 1 100.00
chip_sw_spi_device_pass_through_collision 200.650s 3302.688us 0 1 0.00
chip_sw_gpio 338.580s 4512.794us 1 1 100.00
chip_sw_flash_ctrl_ops 376.070s 4300.322us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 337.050s 3624.598us 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 156.260s 2891.545us 0 1 0.00
chip_sw_flash_ctrl_access 592.400s 5562.400us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 557.210s 6272.764us 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 233.670s 3781.688us 1 1 100.00
chip_sw_flash_init 1197.820s 19397.019us 1 1 100.00
chip_sw_flash_rma_unlocked 3930.290s 44306.121us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 512.120s 5675.863us 1 1 100.00
chip_sw_kmac_entropy 1407.680s 10491.203us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 160.560s 3141.567us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 203.530s 3533.480us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 629.800s 7806.122us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 465.820s 7182.361us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 530.380s 7630.996us 0 1 0.00
chip_sw_otp_ctrl_vendor_test_csr_access 67.850s 3029.695us 1 1 100.00
chip_sw_otp_ctrl_escalation 202.650s 2949.465us 0 1 0.00
chip_sw_otp_ctrl_dai_lock 831.600s 8236.952us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 7.710s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 170.460s 2842.184us 1 1 100.00
chip_sw_otp_ctrl_descrambling 176.110s 3049.416us 1 1 100.00
chip_sw_lc_ctrl_transition 427.350s 7053.639us 1 1 100.00
chip_sw_lc_ctrl_rma_to_scrap 191.270s 3912.763us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 88.570s 3638.934us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 81.110s 3248.991us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 164.920s 3961.418us 1 1 100.00
chip_sw_lc_walkthrough_dev 615.600s 8713.461us 0 1 0.00
chip_sw_lc_walkthrough_prod 671.920s 12304.411us 0 1 0.00
chip_sw_lc_walkthrough_prodend 600.220s 7855.987us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 80.270s 2175.191us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 76.900s 2740.177us 1 1 100.00
chip_sw_lc_walkthrough_rma 316.960s 6749.517us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1561.660s 28721.554us 1 1 100.00
chip_sw_rstmgr_sw_req 336.390s 4878.503us 1 1 100.00
chip_sw_rstmgr_sw_rst 169.260s 3029.970us 1 1 100.00
chip_sw_rstmgr_alert_info 1099.290s 12494.249us 1 1 100.00
chip_sw_rstmgr_cpu_info 446.840s 7515.451us 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 222.270s 6139.716us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 250.650s 3738.096us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 741.400s 8447.957us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1036.740s 11453.535us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 589.960s 13957.405us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 233.670s 5609.597us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1101.680s 13441.866us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 319.750s 7185.884us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 341.610s 5927.516us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 147.660s 3224.436us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 306.440s 6914.301us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1071.840s 16027.296us 0 1 0.00
chip_sw_pwrmgr_sleep_disabled 219.070s 3612.326us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 279.360s 5063.330us 1 1 100.00
chip_sw_rv_timer_irq 126.280s 2487.197us 1 1 100.00
chip_sw_rv_timer_systick_test 5785.840s 38241.436us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 169.340s 3538.346us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 386.840s 5286.454us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 272.980s 6771.797us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1015.480s 24439.971us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 267.090s 4322.107us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2500.230s 20706.528us 1 1 100.00
chip_sw_aon_timer_irq 235.450s 3675.735us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 249.580s 6500.150us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 366.010s 7774.131us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 342.570s 4719.749us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 394.480s 4973.967us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3166.250s 35251.728us 0 1 0.00
chip_sw_otbn_randomness 624.350s 6250.258us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq 3633.760s 17425.763us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3756.530s 19012.004us 1 1 100.00
chip_sw_otbn_mem_scramble 306.970s 4164.419us 1 1 100.00
chip_sw_rv_core_ibex_rnd 461.250s 4800.016us 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 403.580s 4490.539us 1 1 100.00
chip_sw_aes_enc 215.230s 3373.519us 1 1 100.00
chip_sw_aes_enc_jitter_en 178.010s 3139.564us 1 1 100.00
chip_sw_aes_idle 156.530s 2398.360us 1 1 100.00
chip_sw_aes_masking_off 200.660s 3023.416us 1 1 100.00
chip_sw_alert_test 202.320s 3181.383us 0 1 0.00
chip_sw_alert_handler_escalation 347.180s 5480.799us 1 1 100.00
chip_sw_alert_handler_ping_timeout 179.930s 3480.944us 1 1 100.00
chip_sw_alert_handler_ping_ok 775.080s 8062.511us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 9063.180s 254288.152us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 142.800s 3268.947us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.138s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clkoff 1022.770s 8392.471us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1076.150s 8967.317us 1 1 100.00
chip_sw_alert_handler_entropy 162.390s 2686.404us 1 1 100.00
chip_sw_aes_entropy 137.380s 2455.452us 1 1 100.00
chip_sw_entropy_src_kat_test 198.970s 3469.992us 1 1 100.00
chip_sw_edn_auto_mode 489.530s 4316.993us 1 1 100.00
chip_sw_edn_boot_mode 305.320s 3428.031us 1 1 100.00
chip_sw_edn_kat 242.100s 2511.671us 1 1 100.00
chip_sw_edn_sw_mode 968.910s 7983.615us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 574.930s 7771.867us 1 1 100.00
chip_sw_csrng_edn_concurrency 3034.020s 19139.735us 1 1 100.00
chip_sw_csrng_kat_test 174.000s 2982.456us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 190.910s 3107.014us 0 1 0.00
chip_sw_entropy_src_ast_rng_req 126.870s 2292.062us 1 1 100.00
chip_sw_entropy_src_csrng 2251.290s 24433.639us 1 1 100.00
chip_sw_edn_entropy_reqs 626.850s 7186.364us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 759.370s 6857.214us 1 1 100.00
chip_sw_hmac_enc 156.340s 3201.688us 1 1 100.00
chip_sw_hmac_enc_jitter_en 184.000s 3225.172us 1 1 100.00
chip_sw_hmac_enc_idle 166.450s 3235.075us 1 1 100.00
chip_sw_hmac_oneshot 1265.060s 9914.278us 1 1 100.00
chip_sw_hmac_multistream 741.310s 5782.557us 1 1 100.00
chip_sw_keymgr_key_derivation 684.570s 7279.844us 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1667.810s 11977.415us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1212.300s 10946.179us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1136.270s 9251.838us 1 1 100.00
chip_sw_keymgr_sideload_aes 1037.630s 8347.547us 1 1 100.00
chip_sw_keymgr_sideload_otbn 2932.280s 16666.989us 1 1 100.00
chip_sw_kmac_mode_cshake 187.070s 3625.445us 1 1 100.00
chip_sw_kmac_mode_kmac 203.770s 3604.951us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 201.870s 3842.643us 1 1 100.00
chip_sw_kmac_app_rom 127.370s 2477.457us 1 1 100.00
chip_sw_kmac_idle 130.850s 3043.724us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 357.890s 9622.221us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 346.290s 4545.056us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 332.910s 3927.537us 1 1 100.00
chip_sw_sram_ctrl_execution_main 541.020s 8203.461us 1 1 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 418.970s 7291.623us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 410.540s 7202.070us 1 1 100.00
chip_sw_sensor_ctrl_alert 418.790s 5462.439us 1 1 100.00
chip_sw_sensor_ctrl_status 171.620s 3098.712us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 254.460s 5728.095us 1 1 100.00
chip_sw_coremark 9775.610s 72130.570us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1720.340s 21346.081us 1 1 100.00
chip_tl_errors 175.250s 3551.867us 1 1 100.00
chip_prim_tl_access 101.690s 4338.821us 1 1 100.00
chip_plic_all_irqs_0 570.630s 5304.566us 1 1 100.00
chip_plic_all_irqs_10 282.590s 3784.168us 1 1 100.00
chip_plic_all_irqs_20 364.400s 4409.721us 1 1 100.00
chip_sw_plic_sw_irq 146.770s 3042.859us 1 1 100.00
chip_sw_clkmgr_off_peri 918.040s 10051.305us 1 1 100.00
chip_sw_clkmgr_off_aes_trans 348.770s 4789.952us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 323.550s 4856.851us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 283.550s 5114.663us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 285.550s 3784.465us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 536.570s 11953.897us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 377.120s 4350.869us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 420.700s 5068.702us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 372.620s 4048.035us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 390.040s 4981.312us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 371.900s 4622.100us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 363.340s 4641.565us 1 1 100.00
chip_sw_clkmgr_reset_frequency 254.100s 3406.879us 1 1 100.00
chip_sw_clkmgr_jitter_frequency 269.260s 3977.358us 0 1 0.00
chip_sw_clkmgr_jitter 153.280s 2840.323us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 407.770s 5279.649us 1 1 100.00
chip_jtag_csr_rw 564.880s 8977.013us 1 1 100.00
chip_jtag_mem_access 989.170s 13657.739us 1 1 100.00
chip_sw_ast_clk_outputs 593.020s 7446.930us 1 1 100.00
chip_sw_lc_ctrl_program_error 347.650s 5121.813us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 243.520s 7279.544us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 288.240s 4341.575us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 739.490s 23062.167us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1030.140s 26050.503us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.082s 0.000us 0 1 0.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 290.360s 5180.911us 1 1 100.00
chip_rv_dm_ndm_reset_req 246.430s 3921.154us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 219.610s 3348.450us 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 329.960s 5440.763us 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 403.850s 5583.587us 1 1 100.00
chip_tap_straps_dev 141.340s 3618.186us 1 1 100.00
chip_tap_straps_testunlock0 87.930s 2258.339us 1 1 100.00
chip_tap_straps_rma 236.870s 4643.126us 1 1 100.00
chip_tap_straps_prod 88.650s 2654.103us 1 1 100.00
chip_rv_dm_lc_disabled 357.970s 11160.294us 0 1 0.00
chip_sw_rv_core_ibex_address_translation 191.510s 3263.294us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 112.140s 3159.187us 0 1 0.00
chip_sw_rv_core_ibex_icache_invalidate 191.770s 3720.826us 1 1 100.00
chip_sw_usb_ast_clk_calib 199.880s 3789.549us 1 1 100.00
chip_sw_flash_crash_alert 483.000s 6024.944us 1 1 100.00
chip_sw_flash_ctrl_write_clear 185.750s 2866.467us 1 1 100.00
chip_padctrl_attributes 202.620s 5188.946us 1 1 100.00
chip_sw_clkmgr_jitter_reduced_freq 113.880s 3002.156us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 427.210s 5015.610us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 703.120s 7077.427us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4151.640s 25078.163us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 163.630s 2805.414us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 180.560s 3459.377us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1003.130s 10837.170us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 159.580s 3170.933us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 320.520s 4553.355us 1 1 100.00
chip_sw_flash_init_reduced_freq 1326.480s 26319.736us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 3057.700s 24002.115us 1 1 100.00
chip_sw_power_idle_load 211.500s 3368.186us 0 1 0.00
chip_sw_power_sleep_load 144.350s 3321.423us 0 1 0.00
chip_sw_ast_clk_rst_inputs 820.380s 10092.519us 0 1 0.00
chip_sw_power_virus 1118.490s 6894.866us 1 1 100.00
chip_sw_flash_scrambling_smoketest 156.880s 3106.612us 1 1 100.00
chip_sw_flash_ctrl_mem_protection 585.690s 5512.558us 1 1 100.00
ate_bootstrap_flash_erase 613.140s 10010.300us 0 1 0.00
ate_bootstrap_one_frame 6308.010s 45238.190us 1 1 100.00
ate_bootstrap_disjoint 9864.340s 85449.493us 1 1 100.00
rom_e2e_smoke 3183.370s 15202.566us 1 1 100.00
rom_e2e_shutdown_exception_c 2965.810s 15303.388us 1 1 100.00
rom_e2e_shutdown_output 2493.670s 32051.540us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 58.612s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 11.642s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 9.576s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 21.485s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 8.634s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 168.324s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 73.119s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 57.376s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 38.119s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 17.780s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 181.712s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 128.207s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 79.156s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 112.675s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 63.167s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 21.590s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 22.260s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 19.500s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 21.350s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 20.240s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 19.910s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 19.320s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 23.600s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 20.970s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 22.320s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 19.510s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 19.460s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 19.230s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 18.520s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 23.180s 10.160us 0 1 0.00
rom_e2e_asm_init_test_unlocked0 62.102s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 29.305s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 10.473s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 104.022s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 70.961s 0.000us 0 1 0.00
rom_e2e_jtag_debug_test_unlocked0 651.730s 14413.789us 0 1 0.00
rom_e2e_jtag_debug_dev 490.360s 7049.650us 0 1 0.00
rom_e2e_jtag_debug_rma 425.970s 5568.939us 0 1 0.00
rom_e2e_jtag_inject_test_unlocked0 62.300s 2250.971us 0 1 0.00
rom_e2e_jtag_inject_dev 69.340s 2471.255us 0 1 0.00
rom_e2e_jtag_inject_rma 70.990s 2696.925us 0 1 0.00
rom_e2e_static_critical 3103.860s 17016.612us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_meas 5846.280s 30937.236us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 5923.840s 30097.240us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 82.360s 2554.993us 0 1 0.00
rom_volatile_raw_unlock 43.506s 0.000us 0 1 0.00
rom_raw_unlock 46.019s 0.000us 0 1 0.00
rom_e2e_self_hash 63.664s 0.000us 0 1 0.00
rom_keymgr_functest 338.670s 5624.263us 0 1 0.00
chip_sw_aes_smoketest 133.000s 2186.128us 1 1 100.00
chip_sw_aon_timer_smoketest 155.430s 2461.631us 1 1 100.00
chip_sw_clkmgr_smoketest 166.680s 3573.261us 1 1 100.00
chip_sw_csrng_smoketest 126.110s 2791.304us 1 1 100.00
chip_sw_entropy_src_smoketest 755.980s 6347.487us 1 1 100.00
chip_sw_gpio_smoketest 167.140s 2836.225us 1 1 100.00
chip_sw_hmac_smoketest 187.350s 2531.605us 1 1 100.00
chip_sw_kmac_smoketest 233.010s 3465.676us 1 1 100.00
chip_sw_otbn_smoketest 1076.560s 8366.889us 1 1 100.00
chip_sw_otp_ctrl_smoketest 129.220s 3026.325us 1 1 100.00
chip_sw_pwrmgr_smoketest 294.000s 6724.375us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 366.690s 6123.108us 1 1 100.00
chip_sw_rv_plic_smoketest 141.980s 2732.972us 1 1 100.00
chip_sw_rv_timer_smoketest 179.540s 3166.459us 1 1 100.00
chip_sw_rstmgr_smoketest 143.610s 2695.145us 1 1 100.00
chip_sw_sram_ctrl_smoketest 122.990s 2529.957us 1 1 100.00
chip_sw_uart_smoketest 180.600s 2993.501us 1 1 100.00
xbar_smoke 6.320s 217.922us 1 1 100.00
xbar_smoke_zero_delays 4.790s 40.622us 1 1 100.00
xbar_smoke_large_delays 53.530s 7461.135us 1 1 100.00
xbar_smoke_slow_rsp 58.590s 6262.180us 1 1 100.00
xbar_random 29.860s 579.462us 1 1 100.00
xbar_random_zero_delays 10.290s 123.844us 1 1 100.00
xbar_random_large_delays 158.420s 26374.234us 1 1 100.00
xbar_random_slow_rsp 168.110s 17978.293us 1 1 100.00
xbar_access_same_device 29.230s 1101.286us 1 1 100.00
xbar_access_same_device_slow_rsp 696.820s 74702.312us 1 1 100.00
xbar_same_source 54.850s 2718.788us 1 1 100.00
xbar_error_random 17.740s 323.642us 1 1 100.00
xbar_unmapped_addr 7.430s 38.754us 1 1 100.00
xbar_error_and_unmapped_addr 19.990s 650.848us 1 1 100.00
xbar_stress_all 23.980s 1101.881us 1 1 100.00
xbar_stress_all_with_rand_reset 147.570s 2158.751us 1 1 100.00
xbar_stress_all_with_error 87.280s 3755.536us 1 1 100.00
xbar_stress_all_with_reset_error 14.050s 87.210us 1 1 100.00
chip_csr_hw_reset 212.400s 5052.551us 1 1 100.00
chip_csr_rw 287.160s 4805.641us 1 1 100.00
chip_csr_mem_rw_with_rand_reset 73.410s 2432.033us 0 1 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 109543435047136904337671861722207943279383260948403681781461631150252289503420 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 89530714254948778548389352104055792406915942197359582809026127268667825684960 None
Another command (pid=359301) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=385907) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=403184) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 53763407738824712055719522135655830608455730744444207910277096681528669031322 None
Another command (pid=551981) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=450881) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=553056) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 104769199259901174765844017524857424060266460558224866677183071626069597065569 None
---- STDERR ----
Another command (pid=450881) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=553056) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 45607822923345849058850784800654000762002606915241417846998664002432563632782 None
Another command (pid=435847) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=555759) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=545159) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 53145850545744253262357544315317498542841437043161839379966111418351682601622 None
---- STDERR ----
Another command (pid=553056) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 69145240993660149662908273203494933999795018940931806717072126699470618940877 None
Another command (pid=365861) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=599502) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=605501) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 27890511903552374303263534244310045392897193945309163673994126393883935480883 None
Another command (pid=450881) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=553056) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=545729) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 110482100371165369369360563494235640530375406050550291095207121025365827320394 None
Another command (pid=540618) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=450881) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=553056) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 26710933014261528032530569800955754756278516653691795774235915852556234095759 None
Another command (pid=435336) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=466333) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=400319) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 96785639668406786753934337190631242657362437300194533457155780579784460012763 None
Another command (pid=466333) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=400319) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=499828) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 6821084629978677808610427375990565228246994212406445562752474043392865281329 None
Another command (pid=628609) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=630942) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=466084) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 79128659071655926199655870746057550534069049768832642557743253493803480175687 None
Another command (pid=641092) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=625985) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=642858) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 61669141454920206887565923116252273363138118076267245087017011285153459416929 None
Another command (pid=551981) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=450881) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=553056) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 79983461824872577515713163847722733250626918418944353609619947686864238569508 None
Another command (pid=576712) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=564248) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=639528) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 87139426677646690440420939831045438713849185085606817247565380929331919907801 None
---- STDERR ----
Another command (pid=445488) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=400319) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 5913834176954923683733344399680089320298925640420546628774061391730018192241 None
---- STDERR ----
Another command (pid=359301) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=403184) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 67369351344402846355038475967942571107896186840117761928350011340934987569171 None
Another command (pid=433199) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=360298) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=393061) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 42340485221596410255380521711231623491639676456762667408507266983658615580396 None
Another command (pid=360298) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=393061) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=446900) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 68957887475311594081731736118546390138156514521195539148957660409056862689171 None
Another command (pid=565971) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=596854) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=583881) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 86195151165278330232472894802772022252796797422699309076768984064488779732347 None
Another command (pid=415975) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=435336) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=466333) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 51132118369189870209405556804879188778402089130551740695500800534257092962763 None
---- STDERR ----
Another command (pid=359301) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 83283677230257972256157455668560021646045252180458681054805082945764098155395 None
---- STDERR ----
Another command (pid=359301) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=403184) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 103398082155465747475317136351349044616940429532409354573593213065531376414224 None
Another command (pid=433199) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=360298) is running. Waiting for it to complete on the server (server_pid=265415)...
Another command (pid=393061) is running. Waiting for it to complete on the server (server_pid=265415)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 6 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 101487963127196294521733254436621550389031814575694897927458540593779717463183 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 60876159044259986227379448111338006107667609473697759766104787334920201847245 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 41491303823032521930809803755495331209936779488038657891683468690272351614177 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 42327737321756912578741369644875393318723090781428255435651194863731103961559 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 104179325464986466373601979417663865364720437520008248831354212406374170667994 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 50211049029746438884983990777313550742224575891896397167431174867199446091874 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 111932863560813728835543189082417235820368403459400299669261526092542291641186 365
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 92429366714970681513181522699705539566799372335857921244727908058295757731516 365
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 101694081091243180473798849751417580703629592649440399583693409427719590026087 364
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 89795201277619296276810671313308056625059807113960060276383339664760343637274 327
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 91664664261327526717208050858526632069344826829099507623381875423467956663729 326
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 92080562742816865389190748433643269894610451569711050558659234918570248641105 328
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 4 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 80193120111042314154696274900673414559748198865751762488860958287649356029417 344
UVM_ERROR @ 13957.404500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 13957.404500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 8330293258003588727649475868869969176605189046115521912228381520065016021779 314
UVM_ERROR @ 5609.597500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5609.597500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 36438981960058752063670349130331327643420499623109320192302551584605343572273 325
UVM_ERROR @ 7185.884000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7185.884000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 83505745803240396884040511663805872217202415459711165059119119441597183343914 319
UVM_ERROR @ 7774.131000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7774.131000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 86359475277948505758687987412924140984459091164377631768227114733488874442322 369
UVM_INFO @ 8713.461320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 19518974063512154270239619214966932172373559772532457396843276906531849951032 369
UVM_INFO @ 12304.410844 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 68481399705312386899516342356139395709302332530174819730401602024494878529406 341
UVM_INFO @ 6749.517257 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 105991648597220447316879332140989353889618437200831631135096171695449331226172 325
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 75382480878374487424248150577950040948322065060113479902569481394116787961617 326
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 45232106846136116883285057515276237348292998135816459452603550457076319782515 326
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 2 test runs
chip_sw_otp_ctrl_escalation 51954521659498627599028394637655174347635763687588010656713199901499667565870 316
UVM_ERROR @ 2949.465456 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2949.465456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 89071379270400499692085394753965014424651184702125933318156158112484381153704 312
UVM_ERROR @ 3107.014118 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3107.014118 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 2 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 58398451562875333015415661038921871979465013250353074239360683370212670956780 313
UVM_ERROR @ 3224.436000 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3224.436000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 40444207331931757772924457416474615870810460293322043362931446077012148107374 370
UVM_ERROR @ 16027.295970 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 16027.295970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 43329697776571782824627640594908639551670004586733112064553541880538243121332 364
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 104888709016559303406643782045784231585573287806033450775090997190685003906411 325
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 71251837052088542474373552873107804419213822882204245637348321336353733272698 364
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 23004718446924833268118396343496438588022941305903891852643756174834068593240 325
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 71467378424264262024994280729741583155286562482220994320779201450618315764960 301
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] 1 test run
chip_sw_sleep_pin_mio_dio_val 23552060421923413357844121370507227512935227041186840081512134763794199967878 451
UVM_INFO @ 3367.020500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 105972742801860855761400697007205581738015605036472883524457459528967562590792 327
UVM_INFO @ 3302.687870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 74201217228497176079083843115742937919921119634642720656249755712010389515046 309
UVM_INFO @ 2891.544660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 17009377972265234173608590232170341315118002186051537618855702225557899696258 342
UVM_INFO @ 7630.995642 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 67483053798414214023577209738625432879843508356426579046298678796476816416613 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 101360475170008498666483156283936904112487199228352599080235957622201718439797 318
UVM_ERROR @ 6139.716320 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6139.716320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 56914243522556008854774318998871729725829278574216965198271291488615586751532 332
UVM_INFO @ 35251.727699 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:367)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 41272737297108097505345153050694581816620870580100568334439509761237610765235 307
UVM_INFO @ 3181.383266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 34687417269968517631791933223025310829822947990738774971316347756783475389761 308
UVM_INFO @ 3268.947128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 44601737534478957784060413027500120655700686498785445923007509801399160589087 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 89411180708586805287330376760648321498708463772857170580375959676546246966250 343
UVM_INFO @ 3977.358074 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() 1 test run
chip_sw_pwrmgr_lowpower_cancel 113679530035451110148067685609714728925191737170572091881470250431202368591109 317
UVM_INFO @ 4341.574680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 101718776180188700203106488475806120475350262303447100067460082376903008460433 267
UVM_INFO @ 11160.294090 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. 1 test run
chip_sw_rv_core_ibex_lockstep_glitch 105197622844145125512967761721010756703763062473971185659557974236509719209188 331
UVM_INFO @ 3159.186636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_idle_load 37643214151869654068314839980664927904518456193308023552579125268809184601468 314
UVM_INFO @ 3368.186000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_sleep_load 44542757782232027219327918087997887121342870322456822846472347354854736956691 318
UVM_INFO @ 3321.423500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 99937685058817355224814151173320322848431723470828303756266584730464035746253 327
UVM_INFO @ 10092.518993 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 70505285200779891488211126587060989932581670138513126979616022968114321509300 272
UVM_INFO @ 10010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 97540999935031168030289367327358658839620184157024259735570923391145701679528 325
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 51316332361546988478962839682409515779770180002058050429445622930216800122465 325
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! 1 test run
rom_e2e_jtag_debug_test_unlocked0 91971418655624741476047337156296089065059888554869045799484947693724321150253 330
UVM_INFO @ 14413.789375 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(reset_cause == HwReq)' 1 test run
rom_e2e_keymgr_init_rom_ext_invalid_meas 14073845932826185405825617012312061521436411730106165068419933842186969479342 317
UVM_ERROR @ 2554.993104 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 2554.993104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 30841507108451409368160888020745434773772160838587959097876638629588157313964 327
UVM_ERROR @ 5624.263100 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5624.263100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
chip_csr_mem_rw_with_rand_reset 12898678506624072429720698594682053961815201033556672336466535475012797742248 224
TL item was: req: (cip_tl_seq_item@32432) { a_addr: 'h10744 a_data: 'he0039c00 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h19 a_opcode: 'h4 a_user: 'h1bdc2 d_param: 'h0 d_source: 'h19 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2432.033424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---