Simulation Results: i2c

 
28/05/2026 15:30:27 DVSim: v1.49.6 sha: 1d0cf80 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.52 %
  • code
  • 81.61 %
  • assert
  • 97.46 %
  • func
  • 77.48 %
  • line
  • 96.41 %
  • branch
  • 92.33 %
  • cond
  • 85.23 %
  • toggle
  • 89.45 %
  • FSM
  • 44.64 %
Validation stages
unmapped
86.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 43 50 86.00
i2c_host_smoke 38.200s 4556.709us 1 1 100.00
i2c_host_override 0.900s 111.401us 1 1 100.00
i2c_host_fifo_watermark 52.980s 16081.944us 1 1 100.00
i2c_host_fifo_overflow 40.950s 27837.019us 1 1 100.00
i2c_host_fifo_reset_fmt 1.060s 123.068us 1 1 100.00
i2c_host_fifo_fmt_empty 8.850s 971.534us 1 1 100.00
i2c_host_fifo_reset_rx 2.390s 632.488us 1 1 100.00
i2c_host_fifo_full 65.410s 6671.268us 1 1 100.00
i2c_host_perf 3.890s 434.048us 1 1 100.00
i2c_host_perf_precise 26.100s 23631.016us 1 1 100.00
i2c_host_stretch_timeout 5.920s 2022.415us 1 1 100.00
i2c_host_error_intr 0.760s 9.695us 0 1 0.00
i2c_host_stress_all 38.660s 27491.603us 0 1 0.00
i2c_target_glitch 1.850s 719.766us 0 1 0.00
i2c_target_smoke 20.870s 3795.056us 1 1 100.00
i2c_target_stress_wr 15.880s 11156.392us 1 1 100.00
i2c_target_stress_rd 21.510s 3445.711us 1 1 100.00
i2c_target_stretch 29.390s 3664.540us 1 1 100.00
i2c_target_intr_smoke 5.370s 4981.416us 1 1 100.00
i2c_target_intr_stress_wr 6.150s 3939.354us 1 1 100.00
i2c_target_timeout 5.380s 2725.981us 1 1 100.00
i2c_target_unexp_stop 1.190s 66.688us 0 1 0.00
i2c_target_fifo_reset_acq 1.120s 381.719us 1 1 100.00
i2c_target_fifo_reset_tx 1.050s 145.679us 1 1 100.00
i2c_target_perf 2.680s 2245.617us 1 1 100.00
i2c_target_stress_all 44.920s 21795.979us 1 1 100.00
i2c_target_bad_addr 4.730s 2519.201us 1 1 100.00
i2c_target_hrst 23.810s 10128.810us 0 1 0.00
i2c_host_stress_all_with_rand_reset 8.990s 1420.587us 0 1 0.00
i2c_target_stress_all_with_rand_reset 26.920s 1130.679us 0 1 0.00
i2c_host_mode_toggle 4.480s 167.629us 1 1 100.00
i2c_host_may_nack 4.620s 1457.202us 1 1 100.00
i2c_target_fifo_watermarks_acq 2.040s 2038.901us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.470s 159.676us 1 1 100.00
i2c_target_tx_stretch_ctrl 1.490s 72.319us 1 1 100.00
i2c_target_smbus_maxlen 2.620s 2127.053us 1 1 100.00
i2c_target_nack_acqfull 2.300s 445.096us 1 1 100.00
i2c_target_nack_acqfull_addr 2.120s 507.740us 1 1 100.00
i2c_target_nack_txstretch 1.670s 838.739us 1 1 100.00
i2c_tl_errors 2.050s 655.306us 1 1 100.00
i2c_tl_intg_err 2.230s 90.885us 1 1 100.00
i2c_sec_cm 0.900s 71.162us 1 1 100.00
i2c_intr_test 0.870s 48.852us 1 1 100.00
i2c_alert_test 0.880s 143.311us 1 1 100.00
i2c_csr_hw_reset 0.880s 18.876us 1 1 100.00
i2c_csr_rw 0.720s 195.173us 1 1 100.00
i2c_csr_bit_bash 4.060s 2390.217us 1 1 100.00
i2c_csr_aliasing 1.710s 207.709us 1 1 100.00
i2c_same_csr_outstanding 1.220s 55.451us 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.490s 112.640us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 2 test runs
i2c_host_error_intr 21855865283351707562278735124183281359441739331896066300707829596410481041052 80
UVM_INFO @ 9694977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 112756719052109142194258304226199091027161380325922802856409583804717306583500 112
UVM_INFO @ 27491602759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 62086815391710845024419443845071115817708500731724654070315435467985673000911 84
UVM_INFO @ 719766367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 86122257709456354050203142383151072158246111884388299927020289510257729330914 78
UVM_INFO @ 66688026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! 1 test run
i2c_target_hrst 77720485298447493092606518635312783214567381540977801671330816152555305618539 79
UVM_INFO @ 10128809950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 43058734514370124752740947233733341962166539446119203390833174438166536267898 84
UVM_INFO @ 1420587143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1199) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
i2c_target_stress_all_with_rand_reset 106548624506517727522060670962749522179586466425485868085545364340502407667156 96
UVM_INFO @ 1130679354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---