| unmapped |
|
88.89% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 16 | 18 | 88.89 | |||
| pattgen_smoke | 2.000s | 154.769us | 1 | 1 | 100.00 | |
| pattgen_perf | 492.000s | 21004.697us | 1 | 1 | 100.00 | |
| pattgen_error | 2.000s | 326.884us | 1 | 1 | 100.00 | |
| cnt_rollover | 30.000s | 5256.070us | 1 | 1 | 100.00 | |
| pattgen_inactive_level | 2.000s | 177.424us | 1 | 1 | 100.00 | |
| pattgen_tl_errors | 2.000s | 134.114us | 1 | 1 | 100.00 | |
| pattgen_tl_intg_err | 1.000s | 47.689us | 1 | 1 | 100.00 | |
| pattgen_sec_cm | 1.000s | 255.798us | 1 | 1 | 100.00 | |
| pattgen_stress_all_with_rand_reset | 68.000s | 2799.785us | 0 | 1 | 0.00 | |
| pattgen_stress_all | 2.000s | 208.596us | 0 | 1 | 0.00 | |
| pattgen_intr_test | 1.000s | 144.358us | 1 | 1 | 100.00 | |
| pattgen_alert_test | 2.000s | 39.180us | 1 | 1 | 100.00 | |
| pattgen_csr_hw_reset | 1.000s | 61.294us | 1 | 1 | 100.00 | |
| pattgen_csr_rw | 1.000s | 14.987us | 1 | 1 | 100.00 | |
| pattgen_csr_bit_bash | 4.000s | 286.925us | 1 | 1 | 100.00 | |
| pattgen_csr_aliasing | 2.000s | 40.160us | 1 | 1 | 100.00 | |
| pattgen_same_csr_outstanding | 1.000s | 22.649us | 1 | 1 | 100.00 | |
| pattgen_csr_mem_rw_with_rand_reset | 1.000s | 20.907us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_vseq.sv:1287) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 1 test run | |||
| pattgen_stress_all_with_rand_reset | 115527703748613724892254929156118138251264963333584354871129439724937225299793 | 165 |
UVM_ERROR @ 700417775 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 700417775 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 700479629 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] | 1 test run | |||
| pattgen_stress_all | 45953803543973281978869362109757137732984667176071731310189890522858903515416 | 118 |
--> channel 1 item mismatch!
--> EXP:
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