Simulation Results: spi_device/1r1w

 
28/05/2026 15:30:27 DVSim: v1.49.6 sha: 1d0cf80 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.78 %
  • code
  • 93.20 %
  • assert
  • 95.39 %
  • func
  • 74.75 %
  • line
  • 98.89 %
  • branch
  • 98.25 %
  • cond
  • 95.97 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
unmapped
93.94%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 31 33 93.94
spi_device_csb_read 0.730s 13.476us 1 1 100.00
spi_device_mem_parity 0.720s 1.851us 0 1 0.00
spi_device_ram_cfg 0.770s 3.579us 0 1 0.00
spi_device_tpm_read_hw_reg 2.420s 1986.052us 1 1 100.00
spi_device_tpm_all 14.690s 1308.894us 1 1 100.00
spi_device_tpm_sts_read 0.970s 123.476us 1 1 100.00
spi_device_tpm_rw 1.850s 139.558us 1 1 100.00
spi_device_pass_cmd_filtering 4.060s 365.023us 1 1 100.00
spi_device_pass_addr_payload_swap 6.040s 1440.360us 1 1 100.00
spi_device_intercept 4.060s 3964.637us 1 1 100.00
spi_device_mailbox 23.290s 23189.819us 1 1 100.00
spi_device_upload 10.060s 15276.242us 1 1 100.00
spi_device_cfg_cmd 6.860s 4671.711us 1 1 100.00
spi_device_flash_mode 13.820s 5050.268us 1 1 100.00
spi_device_flash_mode_ignore_cmds 99.340s 64849.431us 1 1 100.00
spi_device_read_buffer_direct 3.160s 512.513us 1 1 100.00
spi_device_flash_all 172.920s 39459.290us 1 1 100.00
spi_device_flash_and_tpm 157.250s 150318.435us 1 1 100.00
spi_device_flash_and_tpm_min_idle 67.080s 12193.141us 1 1 100.00
spi_device_stress_all 114.390s 34788.418us 1 1 100.00
spi_device_sec_cm 1.260s 92.406us 1 1 100.00
spi_device_tl_errors 1.850s 1500.887us 1 1 100.00
spi_device_tl_intg_err 6.000s 641.127us 1 1 100.00
spi_device_intr_test 1.070s 35.133us 1 1 100.00
spi_device_alert_test 0.870s 16.775us 1 1 100.00
spi_device_mem_walk 0.690s 34.555us 1 1 100.00
spi_device_mem_partial_access 1.960s 235.325us 1 1 100.00
spi_device_csr_hw_reset 1.360s 45.882us 1 1 100.00
spi_device_csr_rw 1.780s 39.908us 1 1 100.00
spi_device_csr_bit_bash 16.150s 368.273us 1 1 100.00
spi_device_csr_aliasing 5.990s 429.769us 1 1 100.00
spi_device_same_csr_outstanding 2.110s 84.644us 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.700s 57.221us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 81955246915921545711331734863919100985342622143928999346047653033065888972285 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1483181 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1483181 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[950])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 31304590387721649359774637808511234630937922014642801331884932228929997758602 76
UVM_ERROR @ 1087647 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcc7127 [110011000111000100100111] vs 0x0 [0])
UVM_ERROR @ 1096647 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7c2494 [11111000010010010010100] vs 0x0 [0])
UVM_ERROR @ 1103647 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x194d9b [110010100110110011011] vs 0x0 [0])
UVM_ERROR @ 1196647 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3250f2 [1100100101000011110010] vs 0x0 [0])