Simulation Results: chip

 
01/06/2026 15:30:27 DVSim: v1.49.6 sha: 12b260e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 77.68 %
  • code
  • 84.55 %
  • assert
  • 97.25 %
  • func
  • 51.25 %
  • line
  • 94.08 %
  • branch
  • 92.49 %
  • cond
  • 87.81 %
  • toggle
  • 91.24 %
  • FSM
  • 57.14 %
Validation stages
unmapped
76.29%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 251 329 76.29
chip_csr_bit_bash 631.220s 10794.986us 1 1 100.00
chip_csr_aliasing 2865.070s 25664.099us 1 1 100.00
chip_same_csr_outstanding 3045.740s 30787.044us 1 1 100.00
chip_sw_example_flash 134.990s 2770.753us 1 1 100.00
chip_sw_example_rom 76.550s 2432.195us 1 1 100.00
chip_sw_example_manufacturer 130.540s 2886.977us 1 1 100.00
chip_sw_example_concurrency 106.940s 3091.651us 1 1 100.00
chip_sival_flash_info_access 221.240s 3524.179us 1 1 100.00
chip_sw_all_escalation_resets 445.450s 5515.627us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 19.470s 10.300us 0 1 0.00
chip_sw_data_integrity_escalation 341.080s 4812.062us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 167.120s 3767.415us 0 1 0.00
chip_sw_sleep_pin_wake 183.090s 3580.589us 1 1 100.00
chip_sw_sleep_pin_retention 215.510s 3935.483us 1 1 100.00
chip_sw_sleep_pwm_pulses 772.320s 9807.906us 1 1 100.00
chip_sw_pattgen_ios 154.610s 2646.639us 1 1 100.00
chip_sw_uart_tx_rx 404.030s 4466.267us 1 1 100.00
chip_sw_uart_tx_rx_idx1 351.060s 4271.842us 1 1 100.00
chip_sw_uart_tx_rx_idx2 358.540s 3865.495us 1 1 100.00
chip_sw_uart_tx_rx_idx3 363.310s 4510.148us 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7869.040s 62849.832us 1 1 100.00
chip_sw_usbdev_vbus 137.060s 2340.833us 1 1 100.00
chip_sw_usbdev_dpi 1670.760s 12246.035us 1 1 100.00
chip_sw_usbdev_pullup 175.190s 3023.555us 1 1 100.00
chip_sw_usbdev_aon_pullup 272.950s 3685.143us 1 1 100.00
chip_sw_usbdev_setuprx 330.980s 3799.665us 1 1 100.00
chip_sw_usbdev_config_host 969.230s 8699.143us 1 1 100.00
chip_sw_usbdev_pincfg 4682.310s 31578.714us 1 1 100.00
chip_sw_usbdev_stream 3022.550s 18866.581us 1 1 100.00
chip_sw_usbdev_toggle_restore 191.810s 3131.832us 1 1 100.00
chip_sw_inject_scramble_seed 7702.800s 58874.107us 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7092.140s 55937.873us 1 1 100.00
chip_sw_uart_rand_baudrate 871.140s 7508.742us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1662.400s 13239.215us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 632.580s 8511.175us 1 1 100.00
chip_sw_i2c_host_tx_rx 415.670s 5548.889us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 418.740s 6108.225us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 434.580s 4994.988us 1 1 100.00
chip_sw_i2c_device_tx_rx 310.380s 4494.614us 1 1 100.00
chip_sw_spi_device_tpm 217.640s 3678.344us 1 1 100.00
chip_sw_spi_host_tx_rx 223.870s 3080.466us 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 216.240s 3758.959us 1 1 100.00
chip_sw_spi_device_pass_through 230.380s 3052.678us 1 1 100.00
chip_sw_spi_device_pass_through_collision 213.490s 3517.894us 0 1 0.00
chip_sw_gpio 297.530s 4033.010us 1 1 100.00
chip_sw_flash_ctrl_ops 378.240s 4537.504us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 307.390s 3529.805us 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 172.900s 3559.502us 0 1 0.00
chip_sw_flash_ctrl_access 574.560s 5853.716us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 644.630s 6260.941us 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 202.320s 3477.343us 1 1 100.00
chip_sw_flash_init 963.030s 18358.376us 1 1 100.00
chip_sw_flash_rma_unlocked 3370.340s 43408.825us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 525.710s 5630.255us 1 1 100.00
chip_sw_kmac_entropy 822.330s 6963.828us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 126.400s 2583.374us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 191.900s 2643.835us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 411.430s 6912.812us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 603.110s 5850.972us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 502.200s 6384.504us 0 1 0.00
chip_sw_otp_ctrl_vendor_test_csr_access 141.000s 2922.446us 1 1 100.00
chip_sw_otp_ctrl_escalation 187.060s 3477.536us 0 1 0.00
chip_sw_otp_ctrl_dai_lock 733.490s 6771.159us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 6.310s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 154.850s 3212.944us 1 1 100.00
chip_sw_otp_ctrl_descrambling 190.130s 3335.713us 1 1 100.00
chip_sw_lc_ctrl_transition 682.990s 13545.752us 1 1 100.00
chip_sw_lc_ctrl_rma_to_scrap 132.080s 3221.382us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 104.940s 3435.866us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 81.680s 3580.099us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 169.810s 3427.556us 1 1 100.00
chip_sw_lc_walkthrough_dev 670.400s 11012.727us 0 1 0.00
chip_sw_lc_walkthrough_prod 695.470s 8761.454us 0 1 0.00
chip_sw_lc_walkthrough_prodend 584.000s 10513.891us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 92.250s 2974.386us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 57.120s 1867.541us 1 1 100.00
chip_sw_lc_walkthrough_rma 403.230s 6847.634us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1683.100s 33208.328us 1 1 100.00
chip_sw_rstmgr_sw_req 314.310s 4842.497us 1 1 100.00
chip_sw_rstmgr_sw_rst 153.880s 2590.343us 1 1 100.00
chip_sw_rstmgr_alert_info 947.750s 13693.970us 1 1 100.00
chip_sw_rstmgr_cpu_info 321.310s 4766.153us 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 76.130s 2454.039us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 263.690s 3684.079us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 751.380s 8110.921us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1025.350s 11031.901us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1547.160s 23173.235us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 365.140s 10057.052us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 939.590s 12632.136us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 254.650s 7039.142us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 327.140s 6574.816us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 147.920s 2478.108us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 316.700s 8107.410us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 399.200s 8470.166us 0 1 0.00
chip_sw_pwrmgr_sleep_disabled 226.110s 3455.126us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 333.360s 5437.745us 1 1 100.00
chip_sw_rv_timer_irq 162.870s 3286.843us 1 1 100.00
chip_sw_rv_timer_systick_test 5380.120s 38030.256us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 152.230s 2472.888us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 348.000s 4874.251us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 367.410s 6575.129us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1047.000s 24560.674us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 262.410s 4128.552us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2449.690s 20120.230us 1 1 100.00
chip_sw_aon_timer_irq 233.120s 4233.460us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 316.420s 7554.546us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 381.260s 8213.591us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 403.170s 5036.130us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 266.270s 4225.716us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3131.540s 34622.486us 0 1 0.00
chip_sw_otbn_randomness 593.830s 5983.713us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq 3639.470s 17444.548us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3671.390s 19360.352us 1 1 100.00
chip_sw_otbn_mem_scramble 313.370s 4418.106us 1 1 100.00
chip_sw_rv_core_ibex_rnd 522.480s 4684.879us 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 462.790s 5528.449us 1 1 100.00
chip_sw_aes_enc 149.390s 3393.449us 1 1 100.00
chip_sw_aes_enc_jitter_en 140.490s 2620.827us 1 1 100.00
chip_sw_aes_idle 184.680s 3051.211us 1 1 100.00
chip_sw_aes_masking_off 169.680s 2788.683us 1 1 100.00
chip_sw_alert_test 143.530s 2759.067us 0 1 0.00
chip_sw_alert_handler_escalation 311.230s 5804.934us 1 1 100.00
chip_sw_alert_handler_ping_timeout 220.630s 4206.635us 1 1 100.00
chip_sw_alert_handler_ping_ok 712.690s 7504.923us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 7790.090s 255343.113us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 117.640s 2425.303us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.150s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clkoff 801.240s 6802.957us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 876.950s 7511.898us 1 1 100.00
chip_sw_alert_handler_entropy 162.860s 3265.153us 1 1 100.00
chip_sw_aes_entropy 183.120s 3036.361us 1 1 100.00
chip_sw_entropy_src_kat_test 142.470s 2556.008us 1 1 100.00
chip_sw_edn_auto_mode 455.080s 4250.843us 1 1 100.00
chip_sw_edn_boot_mode 294.820s 2912.825us 1 1 100.00
chip_sw_edn_kat 229.430s 2780.317us 1 1 100.00
chip_sw_edn_sw_mode 1300.870s 10486.507us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 459.820s 7473.378us 1 1 100.00
chip_sw_csrng_edn_concurrency 2560.580s 15027.361us 1 1 100.00
chip_sw_csrng_kat_test 142.770s 2804.825us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 164.070s 3407.690us 0 1 0.00
chip_sw_entropy_src_ast_rng_req 121.700s 2535.826us 1 1 100.00
chip_sw_entropy_src_csrng 2185.350s 24865.336us 1 1 100.00
chip_sw_edn_entropy_reqs 559.180s 6381.781us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 545.040s 7659.223us 1 1 100.00
chip_sw_hmac_enc 185.760s 3035.193us 1 1 100.00
chip_sw_hmac_enc_jitter_en 175.130s 2846.634us 1 1 100.00
chip_sw_hmac_enc_idle 172.840s 2748.123us 1 1 100.00
chip_sw_hmac_oneshot 1242.580s 10299.024us 1 1 100.00
chip_sw_hmac_multistream 660.500s 5193.310us 1 1 100.00
chip_sw_keymgr_key_derivation 830.220s 8168.287us 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1680.320s 13122.539us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1054.560s 9952.911us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1754.080s 14242.811us 1 1 100.00
chip_sw_keymgr_sideload_aes 1135.420s 9008.836us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1888.280s 10118.340us 1 1 100.00
chip_sw_kmac_mode_cshake 156.550s 3189.055us 1 1 100.00
chip_sw_kmac_mode_kmac 209.130s 3383.452us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 178.200s 2935.123us 1 1 100.00
chip_sw_kmac_app_rom 147.880s 3236.120us 1 1 100.00
chip_sw_kmac_idle 120.040s 2240.114us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 307.520s 9022.563us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 375.860s 5486.218us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 363.920s 5436.043us 1 1 100.00
chip_sw_sram_ctrl_execution_main 505.570s 7578.425us 1 1 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 377.540s 7045.540us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 552.110s 9467.153us 1 1 100.00
chip_sw_sensor_ctrl_alert 509.540s 7669.659us 1 1 100.00
chip_sw_sensor_ctrl_status 165.850s 3339.773us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 214.760s 4405.995us 1 1 100.00
chip_sw_coremark 9665.760s 71349.626us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1303.140s 28288.860us 1 1 100.00
chip_tl_errors 56.920s 2452.573us 0 1 0.00
chip_prim_tl_access 180.680s 5709.788us 1 1 100.00
chip_plic_all_irqs_0 568.130s 5842.838us 1 1 100.00
chip_plic_all_irqs_10 237.590s 3326.442us 1 1 100.00
chip_plic_all_irqs_20 375.460s 4759.430us 1 1 100.00
chip_sw_plic_sw_irq 147.580s 2985.613us 1 1 100.00
chip_sw_clkmgr_off_peri 645.550s 11042.953us 1 1 100.00
chip_sw_clkmgr_off_aes_trans 298.980s 5193.679us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 309.020s 5122.461us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 242.040s 4159.784us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 264.580s 4767.177us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 310.290s 7622.235us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 357.140s 4629.760us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 339.130s 4305.328us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 327.760s 3990.682us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 383.410s 5134.333us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 398.600s 4213.914us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 333.030s 4810.554us 1 1 100.00
chip_sw_clkmgr_reset_frequency 199.350s 3233.865us 1 1 100.00
chip_sw_clkmgr_jitter_frequency 219.680s 3294.323us 0 1 0.00
chip_sw_clkmgr_jitter 143.890s 2518.556us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 288.430s 4967.790us 1 1 100.00
chip_jtag_csr_rw 594.490s 10028.564us 1 1 100.00
chip_jtag_mem_access 765.410s 13215.295us 1 1 100.00
chip_sw_ast_clk_outputs 458.370s 7032.916us 1 1 100.00
chip_sw_lc_ctrl_program_error 278.340s 5505.965us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 223.020s 7632.370us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 218.230s 3959.254us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 937.530s 22523.087us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1071.820s 23714.441us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 9.293s 0.000us 0 1 0.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 269.550s 6056.437us 1 1 100.00
chip_rv_dm_ndm_reset_req 295.030s 4919.007us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 221.430s 3653.181us 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 325.650s 6064.367us 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 406.260s 5861.358us 1 1 100.00
chip_tap_straps_dev 841.120s 14199.340us 1 1 100.00
chip_tap_straps_testunlock0 336.360s 6139.405us 1 1 100.00
chip_tap_straps_rma 225.260s 4288.123us 1 1 100.00
chip_tap_straps_prod 61.870s 1930.795us 1 1 100.00
chip_rv_dm_lc_disabled 44.320s 2385.576us 0 1 0.00
chip_sw_rv_core_ibex_address_translation 167.400s 3258.680us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 167.690s 2774.622us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 151.310s 2893.403us 1 1 100.00
chip_sw_usb_ast_clk_calib 239.720s 4082.174us 1 1 100.00
chip_sw_flash_crash_alert 333.480s 4635.947us 1 1 100.00
chip_sw_flash_ctrl_write_clear 164.490s 2849.131us 1 1 100.00
chip_padctrl_attributes 195.850s 4816.521us 1 1 100.00
chip_sw_clkmgr_jitter_reduced_freq 125.760s 3224.676us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 354.810s 4870.345us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 622.510s 7436.055us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3807.700s 25379.064us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 130.310s 3196.632us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 160.380s 3490.937us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 639.870s 7275.020us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 185.190s 3161.262us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 388.580s 5470.606us 1 1 100.00
chip_sw_flash_init_reduced_freq 1176.200s 19235.858us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 4118.610s 34969.351us 1 1 100.00
chip_sw_power_idle_load 234.910s 3867.041us 0 1 0.00
chip_sw_power_sleep_load 166.400s 2895.133us 0 1 0.00
chip_sw_ast_clk_rst_inputs 632.140s 9151.742us 0 1 0.00
chip_sw_power_virus 1089.180s 6612.362us 1 1 100.00
chip_sw_flash_scrambling_smoketest 154.410s 2588.759us 1 1 100.00
chip_sw_flash_ctrl_mem_protection 606.280s 5673.504us 1 1 100.00
ate_bootstrap_flash_erase 559.260s 10010.280us 0 1 0.00
ate_bootstrap_one_frame 6131.110s 45412.783us 1 1 100.00
ate_bootstrap_disjoint 9667.490s 84452.208us 1 1 100.00
rom_e2e_smoke 2805.910s 15564.936us 1 1 100.00
rom_e2e_shutdown_exception_c 2830.180s 14900.545us 1 1 100.00
rom_e2e_shutdown_output 2447.350s 24648.669us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 104.446s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 14.512s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 9.981s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 12.653s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 16.149s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 105.017s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 40.015s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 20.697s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 63.279s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 20.312s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 131.135s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 48.459s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 36.763s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 42.721s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 17.392s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 21.650s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 19.430s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 24.320s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 20.230s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 20.440s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 19.830s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 20.080s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 29.380s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 19.630s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 21.410s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 19.250s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 23.620s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 19.260s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 24.730s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 20.260s 10.200us 0 1 0.00
rom_e2e_asm_init_test_unlocked0 40.367s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 36.618s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 36.454s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 71.535s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 36.899s 0.000us 0 1 0.00
rom_e2e_jtag_debug_test_unlocked0 226.170s 4018.135us 0 1 0.00
rom_e2e_jtag_debug_dev 451.200s 5988.104us 0 1 0.00
rom_e2e_jtag_debug_rma 465.740s 6656.752us 0 1 0.00
rom_e2e_jtag_inject_test_unlocked0 73.420s 2920.433us 0 1 0.00
rom_e2e_jtag_inject_dev 80.960s 2726.573us 0 1 0.00
rom_e2e_jtag_inject_rma 68.240s 2123.710us 0 1 0.00
rom_e2e_static_critical 3070.280s 16385.344us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_meas 5674.420s 30892.339us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 3084.090s 18633.377us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 2911.200s 17564.454us 0 1 0.00
rom_volatile_raw_unlock 87.133s 0.000us 0 1 0.00
rom_raw_unlock 14.673s 0.000us 0 1 0.00
rom_e2e_self_hash 26.161s 0.000us 0 1 0.00
rom_keymgr_functest 355.680s 5923.007us 0 1 0.00
chip_sw_aes_smoketest 170.870s 3710.766us 1 1 100.00
chip_sw_aon_timer_smoketest 157.280s 3256.340us 1 1 100.00
chip_sw_clkmgr_smoketest 139.530s 3342.906us 1 1 100.00
chip_sw_csrng_smoketest 111.340s 2706.734us 1 1 100.00
chip_sw_entropy_src_smoketest 706.120s 6480.382us 1 1 100.00
chip_sw_gpio_smoketest 211.890s 3703.856us 1 1 100.00
chip_sw_hmac_smoketest 196.430s 3049.079us 1 1 100.00
chip_sw_kmac_smoketest 206.670s 3534.698us 1 1 100.00
chip_sw_otbn_smoketest 1459.280s 10779.091us 1 1 100.00
chip_sw_otp_ctrl_smoketest 121.400s 2315.259us 1 1 100.00
chip_sw_pwrmgr_smoketest 323.140s 6258.476us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 342.840s 7061.592us 1 1 100.00
chip_sw_rv_plic_smoketest 139.820s 3129.983us 1 1 100.00
chip_sw_rv_timer_smoketest 221.990s 3906.873us 1 1 100.00
chip_sw_rstmgr_smoketest 120.670s 2428.679us 1 1 100.00
chip_sw_sram_ctrl_smoketest 170.170s 3217.414us 1 1 100.00
chip_sw_uart_smoketest 159.480s 2637.194us 1 1 100.00
xbar_smoke 5.890s 164.594us 1 1 100.00
xbar_smoke_zero_delays 4.630s 47.175us 1 1 100.00
xbar_smoke_large_delays 65.170s 9345.794us 1 1 100.00
xbar_smoke_slow_rsp 63.220s 6130.804us 1 1 100.00
xbar_random 22.450s 928.487us 1 1 100.00
xbar_random_zero_delays 16.730s 192.406us 1 1 100.00
xbar_random_large_delays 111.100s 17536.295us 1 1 100.00
xbar_random_slow_rsp 180.310s 19171.646us 1 1 100.00
xbar_access_same_device 98.910s 3857.366us 1 1 100.00
xbar_access_same_device_slow_rsp 524.200s 53973.478us 1 1 100.00
xbar_same_source 14.910s 244.313us 1 1 100.00
xbar_error_random 23.770s 907.484us 1 1 100.00
xbar_unmapped_addr 8.620s 75.961us 1 1 100.00
xbar_error_and_unmapped_addr 10.040s 84.431us 1 1 100.00
xbar_stress_all 11.260s 380.608us 1 1 100.00
xbar_stress_all_with_rand_reset 170.530s 622.643us 1 1 100.00
xbar_stress_all_with_error 127.880s 2541.251us 1 1 100.00
xbar_stress_all_with_reset_error 39.030s 111.723us 1 1 100.00
chip_csr_hw_reset 236.060s 5528.759us 1 1 100.00
chip_csr_rw 448.460s 5780.214us 1 1 100.00
chip_csr_mem_rw_with_rand_reset 51.430s 2735.476us 0 1 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 70541778893032647413245761842408565763004311312328204850352887097659530467378 None
---- STDERR ----
Another command (pid=2088131) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 102848918684255061084041646427711235030898048159987662076345466532306276975658 None
Another command (pid=559740) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=478213) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=457294) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 4531569585630950186630095949045885036322429872412598544664935160371913748235 None
---- STDERR ----
Another command (pid=590101) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 32664362250629849932767935379814823238178843767103548801576380514362152701905 None
---- STDERR ----
Another command (pid=590101) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 10412189779940747300826086015132360218354062292483865252599636484695700666133 None
Another command (pid=570962) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=625506) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=548510) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 899575469757842574463068801511433160253117921377422405451233845206034859119 None
Another command (pid=635232) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=634160) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=636268) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 98364340394071085112491781258090621151997763318059319998679192520057531953419 None
Another command (pid=461587) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=558066) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=440972) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 9122998537928193183252823390685727729341768019973293511998877246524134222090 None
Another command (pid=629409) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=508480) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=634464) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 71482149741311571762091288056517623402944820969122138043999465501725039585168 None
Another command (pid=590101) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=591436) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=556464) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 101462448339984574166284865554271855048164589365720074783950482905192440257990 None
Another command (pid=678021) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=478086) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=703783) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 16831328631105974932176990742929234531067527222304748496366182198459364977358 None
Another command (pid=552460) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=575358) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=590474) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 81778329564968496023270627628606187997637191316000769549924607428223997371512 None
Another command (pid=602558) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=591436) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=556464) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 91080841256645032711060543952745973361073875209276198084429752665966327906856 None
---- STDERR ----
Another command (pid=618272) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 29645820263132158096725847204475228220417392409750567904498224684290951454176 None
Another command (pid=605065) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=594523) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=615684) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 74117272162045672309454247760570802745622202165853044631040271298070799071703 None
Another command (pid=629409) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=611978) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=508480) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 19201453415853355561858026696205646651670859649168863713678761372101233138512 None
Another command (pid=579356) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=583998) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=585314) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 35180600268611103808766547658554557349780703393796668475306084669480385015539 None
Another command (pid=447667) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=396129) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=448833) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 22482585514918899003001099281205996216273743499134179106771570336349904462681 None
---- STDERR ----
Another command (pid=449463) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 19093782798046007145778289566153642252590649783864619431946188737381551878116 None
Another command (pid=472256) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=550438) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=449941) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 77537762171841562843162808590735684935709100005439494256725381702015579181410 None
Another command (pid=641195) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=586866) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=643754) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 78423014209754350586378005237451735955666005373218628196391675957014485106936 None
Another command (pid=567726) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=573077) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=434632) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 102329262322840206171135798340641990448795025666274206705409317242056320315184 None
Another command (pid=487793) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=559740) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=478213) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 1389539347843095384659186148224147115682156744826856645204675871534973430486 None
---- STDERR ----
Another command (pid=396129) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 38546961585465552193803840622870911456538152006761300127493280047449018994926 None
Another command (pid=447667) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=396129) is running. Waiting for it to complete on the server (server_pid=296592)...
Another command (pid=448833) is running. Waiting for it to complete on the server (server_pid=296592)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 7 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 51128138786341670318472369278514689662291850586465873042319544255549029741325 332
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 100999645377130106524501537569047718680383413813124736077990431731223701041653 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 71729572834437978487341277867884407326619712682610190279980930277568544596524 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 1631371708194192936562920543015298927345699033656589950799262036729714105593 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 844727125119426132395745765244507257790165232493255244036956572888795705367 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 51955257785349828633861484874446365515813509321013450688741330244685526768283 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 60577467704858829343436817704485067098505788699736345147239188365790512338434 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 30888793217866418212397083760354638729747493398639318442676960070076562846749 367
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 16186451040663336135531527248324931583299554416934636958693415111993480577656 368
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 23735441956476676271145122229813764529594781835837652043672163779748021333766 367
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 73595340911400052231412332399902630606439313256819295098722301283626123157823 326
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 13097302347513057728942492430674929169120500555991653469848381127955824738210 328
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 74417416030613676676921502111184930745626288977075789161129498365690410244641 328
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 4 test runs
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 47894639414498918876259856023901454763237675155027025489861325703352567575513 332
UVM_ERROR @ 10057.052000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 10057.052000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 49627973074462825254690115897069961424820684998418661068447143216065375430420 330
UVM_ERROR @ 7039.142000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7039.142000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 97983839006468807149536872974127694974574553048900762170565026752955297760965 333
UVM_ERROR @ 8470.166000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8470.166000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 58702220947959686037288308209009498644611368919116421816588741948584733148673 324
UVM_ERROR @ 8213.590500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8213.590500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 84252569341100039334739513712263915851157327290855283994977556616698138469133 369
UVM_INFO @ 11012.726976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 9116643176634943298394368185237926608308528020717135072189471607792948608531 369
UVM_INFO @ 8761.453636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 22405506483565797433310425871531262174657338188355624835676749751301058369367 341
UVM_INFO @ 6847.634394 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 35886085259864381371920241546930407835048832178745309621919916996535213277336 328
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 73156138447802835196416355084497318062828977416794684441910973334943406896627 328
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 112923636605101213448511220143876348004583817446319059208363497929386564479927 328
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 2 test runs
chip_sw_otp_ctrl_escalation 99418036565276489404814858069916743740338259629425147581427937685937491050602 321
UVM_ERROR @ 3477.536476 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3477.536476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 12698177155154132613554108962191204672647061907309682539863998399739335798104 317
UVM_ERROR @ 3407.690088 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3407.690088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 17243857213835836840627509639988269602964746540692274079567457116037795276928 217
TL item was: req: (cip_tl_seq_item@32758) { a_addr: 'h10418 a_data: 'hdc4b71c6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2a a_opcode: 'h4 a_user: 'h1a5ba d_param: 'h0 d_source: 'h2a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2452.573464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 77052700833498933793847481212981519806763124253384677211465011411329115985231 229
TL item was: req: (cip_tl_seq_item@31850) { a_addr: 'h1065c a_data: 'hacca26a0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h20 a_opcode: 'h4 a_user: 'h18ae6 d_param: 'h0 d_source: 'h20 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2735.476298 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 33931113851325788586015384077387997041862997194797722209250047609920002843150 362
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 87788305771521928505700897460751162912234574203081735455120793426791663265868 326
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 12578989166324593053116685181408200100547123138879310327734546628848661450774 365
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 36153279842006557304949238103752098251327443824350410428838063913637279321214 328
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 93067179970583208132222197023155555715533213828390129678300374871760551817746 301
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] 1 test run
chip_sw_sleep_pin_mio_dio_val 113136185625930090381119781404969282191300907014689714334613464051539105344022 456
UVM_INFO @ 3767.415000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 28569215624656988356079690950515463410779884371445469359805631547687634273202 327
UVM_INFO @ 3517.893950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 42906544971800098919053125371463029562840996386171793015676807048871242527570 314
UVM_INFO @ 3559.502204 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 23473451367873575560817556012417000565148333152775133649035099720053486022062 347
UVM_INFO @ 6384.504296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 93270817895839590715726248544249449050253595175033802828253243924711205057006 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 87083505346859658282389162092600660349850680759734819292005701360161227894499 308
UVM_ERROR @ 2454.039336 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2454.039336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 44446907412731471708949767350065762447685668327002333697929845750378605292948 313
UVM_ERROR @ 2478.107735 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2478.107735 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 62046489671530935414944149074300575894056520451439547325826563586613391701990 337
UVM_INFO @ 34622.486329 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 54012584016174666424853836360245923923040824398641267444736860609510256493262 312
UVM_INFO @ 2759.067264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 21823656193002565221869842311882902805890630213653190648640984253531352847421 308
UVM_INFO @ 2425.303248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 74524883919249031706377054313217562172400183104089310267358311764978674329929 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 32391860507143151310616104138573604795137261043538231198116412889870739472451 348
UVM_INFO @ 3294.322639 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 96995999464177949825547911538585069454745315107403997133569845897017345746610 220
UVM_INFO @ 2385.576168 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_idle_load 2182185030931778700024910606567121240051615454174105117074513534277190934566 317
UVM_INFO @ 3867.041000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_sleep_load 24540588997418055273457352256831360745619621735665774683582687268443442078594 323
UVM_INFO @ 2895.133000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 12988454685702818544951451567448900798909299590860892743983659809457882062189 332
UVM_INFO @ 9151.742472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 7804292978901394898243565747049327172778377646700058689020727233506924643862 272
UVM_INFO @ 10010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 28176421835640063161929671249152037378013102387294913801308299926301884669866 325
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 3279004603301218040218136737146051533671202267357575531737945620428542098813 328
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_no_meas 70865993274899156520000949056666979045904454648757117439469565105104610696553 319
UVM_INFO @ 18633.376632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_invalid_meas 113112462922035426738520966371175994985226057436310810493679505184633378817486 319
UVM_INFO @ 17564.454075 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 78103017202054981038467749698947024776560237349996747922240382917230078772239 332
UVM_ERROR @ 5923.007445 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5923.007445 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---