| unmapped |
|
88.89% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 16 | 18 | 88.89 | |||
| pattgen_smoke | 1.000s | 34.040us | 1 | 1 | 100.00 | |
| pattgen_perf | 509.000s | 98438.979us | 1 | 1 | 100.00 | |
| pattgen_error | 1.000s | 142.266us | 1 | 1 | 100.00 | |
| cnt_rollover | 61.000s | 10520.279us | 1 | 1 | 100.00 | |
| pattgen_inactive_level | 15.000s | 10008.956us | 0 | 1 | 0.00 | |
| pattgen_tl_errors | 2.000s | 222.205us | 1 | 1 | 100.00 | |
| pattgen_tl_intg_err | 2.000s | 262.352us | 1 | 1 | 100.00 | |
| pattgen_sec_cm | 1.000s | 39.696us | 1 | 1 | 100.00 | |
| pattgen_stress_all_with_rand_reset | 87.000s | 9469.551us | 0 | 1 | 0.00 | |
| pattgen_stress_all | 5.000s | 278.261us | 1 | 1 | 100.00 | |
| pattgen_intr_test | 1.000s | 15.699us | 1 | 1 | 100.00 | |
| pattgen_alert_test | 2.000s | 45.892us | 1 | 1 | 100.00 | |
| pattgen_csr_hw_reset | 1.000s | 25.486us | 1 | 1 | 100.00 | |
| pattgen_csr_rw | 1.000s | 36.919us | 1 | 1 | 100.00 | |
| pattgen_csr_bit_bash | 2.000s | 375.571us | 1 | 1 | 100.00 | |
| pattgen_csr_aliasing | 1.000s | 68.110us | 1 | 1 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 53.988us | 1 | 1 | 100.00 | |
| pattgen_csr_mem_rw_with_rand_reset | 1.000s | 22.772us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) | 1 test run | |||
| pattgen_inactive_level | 43716571053701107694284108436522402258323142921452443959799368443546619375804 | 99 |
UVM_INFO @ 10008955684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1287) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 1 test run | |||
| pattgen_stress_all_with_rand_reset | 102785274135633208041588725228780346726849791867069798334684146684851330418565 | 131 |
UVM_ERROR @ 1963122206 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1963122206 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1963322206 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
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