Simulation Results: spi_device/1r1w

 
01/06/2026 15:30:27 DVSim: v1.49.6 sha: 12b260e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.53 %
  • code
  • 92.97 %
  • assert
  • 95.39 %
  • func
  • 59.23 %
  • line
  • 98.80 %
  • branch
  • 98.04 %
  • cond
  • 95.13 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
unmapped
93.94%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 31 33 93.94
spi_device_csb_read 0.750s 18.108us 1 1 100.00
spi_device_mem_parity 0.700s 1.850us 0 1 0.00
spi_device_ram_cfg 0.680s 5.891us 0 1 0.00
spi_device_tpm_read_hw_reg 5.390s 1774.195us 1 1 100.00
spi_device_tpm_all 11.880s 1725.095us 1 1 100.00
spi_device_tpm_sts_read 0.840s 116.537us 1 1 100.00
spi_device_tpm_rw 1.130s 45.317us 1 1 100.00
spi_device_pass_cmd_filtering 38.960s 83676.292us 1 1 100.00
spi_device_pass_addr_payload_swap 4.700s 1007.368us 1 1 100.00
spi_device_intercept 14.900s 10758.265us 1 1 100.00
spi_device_mailbox 40.280s 28859.395us 1 1 100.00
spi_device_upload 4.940s 3542.167us 1 1 100.00
spi_device_cfg_cmd 1.690s 258.568us 1 1 100.00
spi_device_flash_mode 13.760s 3493.651us 1 1 100.00
spi_device_flash_mode_ignore_cmds 15.690s 2946.922us 1 1 100.00
spi_device_read_buffer_direct 3.470s 1120.210us 1 1 100.00
spi_device_flash_all 0.870s 103.026us 1 1 100.00
spi_device_flash_and_tpm 327.160s 124196.981us 1 1 100.00
spi_device_flash_and_tpm_min_idle 23.130s 2685.854us 1 1 100.00
spi_device_stress_all 0.940s 278.094us 1 1 100.00
spi_device_sec_cm 1.260s 226.299us 1 1 100.00
spi_device_tl_errors 1.810s 118.976us 1 1 100.00
spi_device_tl_intg_err 6.120s 324.267us 1 1 100.00
spi_device_intr_test 0.730s 13.574us 1 1 100.00
spi_device_alert_test 0.760s 24.494us 1 1 100.00
spi_device_mem_walk 0.680s 41.917us 1 1 100.00
spi_device_mem_partial_access 1.520s 48.856us 1 1 100.00
spi_device_csr_hw_reset 0.990s 36.706us 1 1 100.00
spi_device_csr_rw 1.320s 108.624us 1 1 100.00
spi_device_csr_bit_bash 10.140s 2163.675us 1 1 100.00
spi_device_csr_aliasing 10.580s 747.037us 1 1 100.00
spi_device_same_csr_outstanding 1.500s 133.353us 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.000s 596.048us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 28418411084632806424237635771410508840579604991279927706505550508914407772637 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1255353 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1255353 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[995])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 4026035560951334317450719051911547471274093967644265106839438872331604566148 76
UVM_ERROR @ 3738894 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb55149 [101101010101000101001001] vs 0x0 [0])
UVM_ERROR @ 3778894 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3ca774 [1111001010011101110100] vs 0x0 [0])
UVM_ERROR @ 3839894 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8e73a1 [100011100111001110100001] vs 0x0 [0])
UVM_ERROR @ 3934894 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc2decc [110000101101111011001100] vs 0x0 [0])