Simulation Results: uart

 
01/06/2026 15:30:27 DVSim: v1.49.6 sha: 12b260e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.67 %
  • code
  • 95.96 %
  • assert
  • 98.85 %
  • func
  • 59.19 %
  • line
  • 99.17 %
  • branch
  • 96.97 %
  • cond
  • 96.15 %
  • toggle
  • 91.55 %
Validation stages
unmapped
96.30%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 26 27 96.30
uart_smoke 1.280s 549.614us 1 1 100.00
uart_tx_rx 52.030s 40601.884us 1 1 100.00
uart_fifo_full 8.010s 21033.269us 1 1 100.00
uart_fifo_overflow 33.390s 29220.689us 1 1 100.00
uart_fifo_reset 119.040s 47070.769us 1 1 100.00
uart_rx_oversample 9.280s 5029.609us 1 1 100.00
uart_intr 26.110s 38709.731us 1 1 100.00
uart_noise_filter 22.250s 27961.055us 0 1 0.00
uart_rx_start_bit_filter 1.890s 739.223us 1 1 100.00
uart_rx_parity_err 31.640s 70561.775us 1 1 100.00
uart_tx_ovrd 1.390s 1474.125us 1 1 100.00
uart_loopback 4.360s 10245.124us 1 1 100.00
uart_perf 294.220s 16542.447us 1 1 100.00
uart_long_xfer_wo_dly 224.280s 67974.223us 1 1 100.00
uart_stress_all_with_rand_reset 86.940s 19161.527us 1 1 100.00
uart_stress_all 353.590s 142921.267us 1 1 100.00
uart_sec_cm 1.070s 258.429us 1 1 100.00
uart_tl_errors 1.650s 265.141us 1 1 100.00
uart_tl_intg_err 1.250s 100.195us 1 1 100.00
uart_intr_test 0.600s 45.406us 1 1 100.00
uart_alert_test 0.580s 14.635us 1 1 100.00
uart_csr_hw_reset 0.710s 67.022us 1 1 100.00
uart_csr_rw 0.620s 22.320us 1 1 100.00
uart_csr_bit_bash 1.140s 135.935us 1 1 100.00
uart_csr_aliasing 0.880s 75.906us 1 1 100.00
uart_same_csr_outstanding 0.980s 137.819us 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.660s 18.782us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 29537406198494698710572375474108818672281497197493679582513953945253906528170 80
UVM_ERROR @ 27938034370 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 27938462938 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 27938871098 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 27939462930 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0