Simulation Results: spi_device/1r1w

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.09 %
  • code
  • 93.13 %
  • assert
  • 95.39 %
  • func
  • 60.76 %
  • line
  • 98.78 %
  • branch
  • 98.04 %
  • cond
  • 95.93 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
87.50%
V2
85.19%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
spi_device_flash_and_tpm 121.090s 20457.482us 0 1 0.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.880s 24.885us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.960s 117.757us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 9.300s 4337.333us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.790s 1423.904us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.660s 219.113us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.960s 117.757us 1 1 100.00
spi_device_csr_aliasing 5.790s 1423.904us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.620s 10.262us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 0.910s 18.184us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.710s 16.629us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.700s 1.333us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.760s 8.245us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.920s 25.160us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.920s 25.160us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 5.810s 10267.998us 1 1 100.00
spi_device_tpm_sts_read 0.920s 86.483us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 11.140s 4508.132us 1 1 100.00
pass_cmd_filtering 1 2 50.00
spi_device_pass_cmd_filtering 26.390s 33402.479us 1 1 100.00
spi_device_flash_all 103.120s 216862.831us 0 1 0.00
pass_addr_translation 1 2 50.00
spi_device_pass_addr_payload_swap 2.240s 218.884us 1 1 100.00
spi_device_flash_all 103.120s 216862.831us 0 1 0.00
pass_payload_translation 1 2 50.00
spi_device_pass_addr_payload_swap 2.240s 218.884us 1 1 100.00
spi_device_flash_all 103.120s 216862.831us 0 1 0.00
cmd_info_slots 0 1 0.00
spi_device_flash_all 103.120s 216862.831us 0 1 0.00
cmd_read_status 1 2 50.00
spi_device_intercept 5.760s 931.261us 1 1 100.00
spi_device_flash_all 103.120s 216862.831us 0 1 0.00
cmd_read_jedec 1 2 50.00
spi_device_intercept 5.760s 931.261us 1 1 100.00
spi_device_flash_all 103.120s 216862.831us 0 1 0.00
cmd_read_sfdp 1 2 50.00
spi_device_intercept 5.760s 931.261us 1 1 100.00
spi_device_flash_all 103.120s 216862.831us 0 1 0.00
cmd_fast_read 1 2 50.00
spi_device_intercept 5.760s 931.261us 1 1 100.00
spi_device_flash_all 103.120s 216862.831us 0 1 0.00
cmd_read_pipeline 1 2 50.00
spi_device_intercept 5.760s 931.261us 1 1 100.00
spi_device_flash_all 103.120s 216862.831us 0 1 0.00
flash_cmd_upload 1 1 100.00
spi_device_upload 17.080s 8255.406us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 14.390s 2961.485us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 14.390s 2961.485us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 14.390s 2961.485us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 8.330s 4523.847us 1 1 100.00
spi_device_read_buffer_direct 12.330s 7419.613us 1 1 100.00
cmd_dummy_cycle 1 2 50.00
spi_device_mailbox 14.390s 2961.485us 1 1 100.00
spi_device_flash_all 103.120s 216862.831us 0 1 0.00
quad_spi 0 1 0.00
spi_device_flash_all 103.120s 216862.831us 0 1 0.00
dual_spi 0 1 0.00
spi_device_flash_all 103.120s 216862.831us 0 1 0.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 1.950s 270.151us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 1.950s 270.151us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 211.040s 52093.007us 1 1 100.00
TPM_with_flash_or_passthrough_mode 0 1 0.00
spi_device_flash_and_tpm 121.090s 20457.482us 0 1 0.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 92.590s 9785.072us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 1.270s 105.744us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.650s 14.140us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.790s 44.881us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.960s 140.662us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.960s 140.662us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.880s 24.885us 1 1 100.00
spi_device_csr_rw 1.960s 117.757us 1 1 100.00
spi_device_csr_aliasing 5.790s 1423.904us 1 1 100.00
spi_device_same_csr_outstanding 1.770s 140.421us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.880s 24.885us 1 1 100.00
spi_device_csr_rw 1.960s 117.757us 1 1 100.00
spi_device_csr_aliasing 5.790s 1423.904us 1 1 100.00
spi_device_same_csr_outstanding 1.770s 140.421us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.960s 189.721us 1 1 100.00
spi_device_tl_intg_err 5.550s 341.540us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.550s 341.540us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 83550188316143628779656766736561601187657939977570304535188816375865369585089 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1153121 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1153121 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[939])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 79970619159903919014383155849472380135169701863392030959830694733712993211390 76
UVM_ERROR @ 6102628 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x55a5d0 [10101011010010111010000] vs 0x0 [0])
UVM_ERROR @ 6195628 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd1d044 [110100011101000001000100] vs 0x0 [0])
UVM_ERROR @ 6198628 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x28126d [1010000001001001101101] vs 0x0 [0])
UVM_ERROR @ 6257628 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5e16ab [10111100001011010101011] vs 0x0 [0])
UVM_ERROR (spi_device_pass_base_vseq.sv:705) [spi_device_flash_all_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * 1 test run
spi_device_flash_all 107806280488645975782453202948845969067731007590557701998130442751021368318438 118
tl_ul_fuzzy_flash_status_q[i] = 0x832b78
tl_ul_fuzzy_flash_status_q[i] = 0x832b78
tl_ul_fuzzy_flash_status_q[i] = 0xf482ec
tl_ul_fuzzy_flash_status_q[i] = 0x24df78
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp * 1 test run
spi_device_flash_and_tpm 113121601849830094006027886777030556401571136850987462742597003562772712071039 99
UVM_INFO @ 14795871846 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/7
UVM_INFO @ 15007142846 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 4/7
UVM_INFO @ 15007142846 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 5/7
tl_ul_fuzzy_flash_status_q[i] = 0x957852