Simulation Results: uart

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.52 %
  • code
  • 95.76 %
  • assert
  • 97.12 %
  • func
  • 48.68 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.10 %
  • toggle
  • 91.32 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.160s 274.317us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.620s 54.312us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.700s 41.427us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.190s 324.626us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.850s 25.280us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.870s 26.751us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.700s 41.427us 1 1 100.00
uart_csr_aliasing 0.850s 25.280us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 8.320s 39797.130us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.160s 274.317us 1 1 100.00
uart_tx_rx 8.320s 39797.130us 1 1 100.00
parity_error 2 2 100.00
uart_intr 11.070s 22349.004us 1 1 100.00
uart_rx_parity_err 63.100s 102430.051us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 8.320s 39797.130us 1 1 100.00
uart_intr 11.070s 22349.004us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 84.500s 326396.311us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 6.890s 4829.456us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 29.470s 107056.796us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 11.070s 22349.004us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 11.070s 22349.004us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 11.070s 22349.004us 1 1 100.00
perf 1 1 100.00
uart_perf 121.310s 5438.136us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 6.570s 3793.376us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 6.570s 3793.376us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 0.800s 72.273us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.160s 3408.947us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.970s 2549.658us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 29.870s 6082.405us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 247.660s 155676.814us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 4.500s 22293.287us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.590s 16.251us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.590s 41.158us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.380s 193.697us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.380s 193.697us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.620s 54.312us 1 1 100.00
uart_csr_rw 0.700s 41.427us 1 1 100.00
uart_csr_aliasing 0.850s 25.280us 1 1 100.00
uart_same_csr_outstanding 0.890s 119.834us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.620s 54.312us 1 1 100.00
uart_csr_rw 0.700s 41.427us 1 1 100.00
uart_csr_aliasing 0.850s 25.280us 1 1 100.00
uart_same_csr_outstanding 0.890s 119.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.170s 79.045us 1 1 100.00
uart_tl_intg_err 1.040s 211.755us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.040s 211.755us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 3.850s 489.159us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 2 test runs
uart_noise_filter 65861425037610924411513099725654041267717508637723810271098092767518334240580 74
UVM_ERROR @ 13953446 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 15153446 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 16073446 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 18073446 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all_with_rand_reset 66142419538161928657896001368300736414820916361319436492487049974115483212547 83
UVM_ERROR @ 472212314 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 472507042 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 472885978 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 473264914 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_stress_all 28443918918868183256076949742578178910787822650511598295939798270644256898227 79
UVM_ERROR @ 13523661421 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 13523716977 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (123 [0x7b] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 14936783837 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 12, clk_pulses: 0
UVM_ERROR @ 14936894949 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty