| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
88.00% |
| V3 |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| otbn_smoke | 10.000s | 56.251us | 1 | 1 | 100.00 | |
| single_binary | 1 | 1 | 100.00 | |||
| otbn_single | 24.000s | 71.345us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| otbn_csr_hw_reset | 34.000s | 45.775us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| otbn_csr_rw | 34.000s | 75.591us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| otbn_csr_bit_bash | 36.000s | 116.189us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| otbn_csr_aliasing | 37.000s | 30.529us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| otbn_csr_mem_rw_with_rand_reset | 37.000s | 140.346us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| otbn_csr_rw | 34.000s | 75.591us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 37.000s | 30.529us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| otbn_mem_walk | 80.000s | 6561.710us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| otbn_mem_partial_access | 53.000s | 16068.221us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_recovery | 1 | 1 | 100.00 | |||
| otbn_reset | 25.000s | 88.347us | 1 | 1 | 100.00 | |
| multi_error | 1 | 1 | 100.00 | |||
| otbn_multi_err | 52.000s | 780.822us | 1 | 1 | 100.00 | |
| back_to_back | 1 | 1 | 100.00 | |||
| otbn_multi | 103.000s | 1256.773us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| otbn_stress_all | 33.000s | 213.908us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| otbn_escalate | 41.000s | 699.383us | 1 | 1 | 100.00 | |
| zero_state_err_urnd | 1 | 1 | 100.00 | |||
| otbn_zero_state_err_urnd | 6.000s | 23.886us | 1 | 1 | 100.00 | |
| sw_errs_fatal_chk | 1 | 1 | 100.00 | |||
| otbn_sw_errs_fatal_chk | 21.000s | 262.729us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| otbn_alert_test | 35.000s | 27.588us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| otbn_intr_test | 19.000s | 14.798us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 5.000s | 279.149us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 5.000s | 279.149us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 34.000s | 45.775us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 34.000s | 75.591us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 37.000s | 30.529us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 6.000s | 42.664us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 34.000s | 45.775us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 34.000s | 75.591us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 37.000s | 30.529us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 6.000s | 42.664us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mem_integrity | 2 | 2 | 100.00 | |||
| otbn_imem_err | 31.000s | 26.945us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 36.000s | 29.768us | 1 | 1 | 100.00 | |
| internal_integrity | 3 | 4 | 75.00 | |||
| otbn_alu_bignum_mod_err | 41.000s | 62.600us | 1 | 1 | 100.00 | |
| otbn_controller_ispr_rdata_err | 2.140s | 0.000us | 0 | 1 | 0.00 | |
| otbn_mac_bignum_acc_err | 22.000s | 73.068us | 1 | 1 | 100.00 | |
| otbn_urnd_err | 4.000s | 29.263us | 1 | 1 | 100.00 | |
| illegal_bus_access | 1 | 1 | 100.00 | |||
| otbn_illegal_mem_acc | 31.000s | 47.773us | 1 | 1 | 100.00 | |
| otbn_mem_gnt_acc_err | 1 | 1 | 100.00 | |||
| otbn_mem_gnt_acc_err | 20.000s | 49.348us | 1 | 1 | 100.00 | |
| otbn_non_sec_partial_wipe | 1 | 1 | 100.00 | |||
| otbn_partial_wipe | 10.000s | 183.141us | 1 | 1 | 100.00 | |
| tl_intg_err | 1 | 2 | 50.00 | |||
| otbn_sec_cm | 203.000s | 1183.933us | 0 | 1 | 0.00 | |
| otbn_tl_intg_err | 21.000s | 1369.114us | 1 | 1 | 100.00 | |
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| otbn_passthru_mem_tl_intg_err | 63.000s | 254.795us | 1 | 1 | 100.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 203.000s | 1183.933us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 203.000s | 1183.933us | 0 | 1 | 0.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| otbn_smoke | 10.000s | 56.251us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_dmem_err | 36.000s | 29.768us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_imem_err | 31.000s | 26.945us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| otbn_tl_intg_err | 21.000s | 1369.114us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 41.000s | 699.383us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 31.000s | 26.945us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 36.000s | 29.768us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 6.000s | 23.886us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 31.000s | 47.773us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 203.000s | 1183.933us | 0 | 1 | 0.00 | |
| sec_cm_controller_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 203.000s | 1183.933us | 0 | 1 | 0.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 24.000s | 71.345us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 31.000s | 26.945us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 36.000s | 29.768us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 6.000s | 23.886us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 31.000s | 47.773us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 203.000s | 1183.933us | 0 | 1 | 0.00 | |
| sec_cm_scramble_ctrl_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 203.000s | 1183.933us | 0 | 1 | 0.00 | |
| sec_cm_start_stop_ctrl_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 41.000s | 699.383us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 31.000s | 26.945us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 36.000s | 29.768us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 6.000s | 23.886us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 31.000s | 47.773us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 203.000s | 1183.933us | 0 | 1 | 0.00 | |
| sec_cm_start_stop_ctrl_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 203.000s | 1183.933us | 0 | 1 | 0.00 | |
| sec_cm_data_reg_sw_sca | 1 | 1 | 100.00 | |||
| otbn_single | 24.000s | 71.345us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_redun | 1 | 1 | 100.00 | |||
| otbn_ctrl_redun | 37.000s | 24.075us | 1 | 1 | 100.00 | |
| sec_cm_pc_ctrl_flow_redun | 1 | 1 | 100.00 | |||
| otbn_pc_ctrl_flow_redun | 8.000s | 24.014us | 1 | 1 | 100.00 | |
| sec_cm_rnd_bus_consistency | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 117.000s | 414.052us | 1 | 1 | 100.00 | |
| sec_cm_rnd_rng_digest | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 117.000s | 414.052us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_base_intg_err | 6.000s | 50.319us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_glitch_detect | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 203.000s | 1183.933us | 0 | 1 | 0.00 | |
| sec_cm_stack_wr_ptr_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 203.000s | 1183.933us | 0 | 1 | 0.00 | |
| sec_cm_rf_bignum_data_reg_sw_integrity | 0 | 1 | 0.00 | |||
| otbn_rf_bignum_intg_err | 0.751s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_rf_bignum_data_reg_sw_glitch_detect | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 203.000s | 1183.933us | 0 | 1 | 0.00 | |
| sec_cm_loop_stack_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 203.000s | 1183.933us | 0 | 1 | 0.00 | |
| sec_cm_loop_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 22.000s | 115.967us | 1 | 1 | 100.00 | |
| sec_cm_call_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 22.000s | 115.967us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_state_consistency | 1 | 1 | 100.00 | |||
| otbn_sec_wipe_err | 7.000s | 57.938us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 24.000s | 71.345us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 24.000s | 71.345us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 24.000s | 71.345us | 1 | 1 | 100.00 | |
| sec_cm_write_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_multi | 103.000s | 1256.773us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_count | 1 | 1 | 100.00 | |||
| otbn_single | 24.000s | 71.345us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_sca | 1 | 1 | 100.00 | |||
| otbn_single | 24.000s | 71.345us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sw_noaccess | 1 | 1 | 100.00 | |||
| otbn_sw_no_acc | 10.000s | 58.821us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 24.000s | 71.345us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 203.000s | 1183.933us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| otbn_stress_all_with_rand_reset | 228.000s | 3013.916us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| otbn_smoke_vectorized | 7.000s | 196.256us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 2 test runs | |||
| otbn_controller_ispr_rdata_err | 90356553999854643552835691313979865785646266305307136214829535041126894445273 | None |
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
|
|
| otbn_rf_bignum_intg_err | 728825267793716969940509156843768251437217041431773845752544646439721167917 | None |
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn_rnd.sv,233): Assertion UrndNoReseedOnReset_A has failed | 1 test run | |||
| otbn_sec_cm | 98796637716170840220079832420487018693185803152914848187106991736423545318446 | 931 |
UVM_ERROR @ 1183933484 ps: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 1183933484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|